Usage Notes and Known Design Exceptions to Functional Specifications
3.1.3
Boot: USB Boot ROM Code Uses Default DATAPOLARITY
The AM335x USB PHYs supports a DATAPOLARITY feature that allows the data plus (DP) and data
minus (DM) data signals to be swapped. This feature was added to simplify PCB layout.
In some cases, the DP and DM data signals may need to cross over each other to connect to the
respective USB connector pins. Crossing these signals on the PCB may cause signal integrity issues if not
implemented properly since they must be routed as high-speed differential transmission lines. The
DATAPOLARITY feature in the USB PHYs can be used resolve this issue.
The DATAPOLARITY feature is controlled by DATAPOLARITY_INV (bit 23) of the respective USB_CTRL
register.
The USB boot ROM code uses the default value for DATAPOLARITY_INV when booting from USB.
Therefore, the PCB must be designed to use the default DATAPOLARITY if the system must support USB
boot.
3.1.4
Boot: Multiplexed Signals GPMC_WAIT0, GMII2_CRS, and RMII2_CRS_DV Cause NAND Boot
Issue
The AM335x device multiplexes the GPMC_WAIT0, GMII2_CRS, and RMII2_CRS_DV signals on the
same terminal. This causes a problem when the system must support NAND boot while an MII or RMII
Ethernet PHY is connected to port 2 of the Ethernet media access controller and switch (CPSW). The
GPMC_WAIT0 signal is required for NAND boot. The GMII2_CRS or RMII2_CRS_DV signal is required by
the respective MII or RMII Ethernet PHY and the only pin multiplexing option for these signals is
GPMC_WAIT0.
In this case, there are two sources that need to be connected to the GPMC_WAIT0 terminal. The NAND
READY or BUSY output must source the GPMC_WAIT0 terminal during NAND boot and the MII CRS or
RMII CRS_DV output must source the GPMC_WAIT0 terminal when the application software is using port
2 of the CPSW. Therefore, a GPIO-controlled external 2-to-1 multiplexer must be implemented in the
system to select between the two sources. The GPIO selected to control the 2-to-1 multiplexer needs to
have an internal or external resistor that selects the NAND READY or BUSY output as soon as power is
applied and remains in that state until the application software initializes the CPSW.
The TI TS5A3157 SPDT analog switch is an example device that can be used as a 2-to-1 multiplexer.
This device inserts minimum propagation delay to the signal path since it is an analog switch. The
propagation delay inserted by the 2-to-1 multiplexer must be analyzed to confirm it does not cause timing
violations for the respective interface.
The NAND, Ethernet PHY, AM335x VDDSHV1, AM335x VDDSHV3 (when using the ZCZ package), and
2-to-1 multiplexer IO power supply domains may need to operate at the same voltage since they share
common signals.
9
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
