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Usage Notes and Known Design Exceptions to Functional Specifications
Advisory 1.0.15
ARM Cortex-A8: OPP50 Operation on MPU Domain Not Supported
Revisions Affected
1.0
Details
Reliability tests have shown that a logic cell used in the ARM Cortex-A8 exhibits
weakness during low-voltage operation as defined by OPP50. This eliminates support for
operating the ARM Cortex-A8 at the lower voltage defined by OPP50. Therefore, the
minimum voltage limit for the ARM Cortex-A8 power terminals (VDD_MPU on the ZCZ
package and VDD_CORE on the ZCE package) is the minimum voltage limit defined by
OPP100.
Workarounds
To minimize power consumption, the ARM Cortex-A8 may be operated at the lower
frequencies defined by OPP50, but the respective power terminal (VDD_MPU for ZCZ
package and VDD_CORE for ZCE package) must be operated as defined by OPP100.
Table 5 below provides register settings for operating the MPU PLL at 275 MHz for each
supported input clock frequency.
Table 5. MPU PLL
CLK_M_OSC N REFCLK M M2 CLKOUT
(MHz) CM_CLKSEL_DPLL_MPU[6:0] (MHz) CM_CLKSEL_DPLL_MPU[18:8] CM_DIV_M2_DPLL_MPU[4:0] (MHz)
19.2 95 0.2 1375 1 275
24 23 1 275 1 275
25 24 1 275 1 275
26 25 1 275 1 275
Advisory 1.0.16
RMII: 50-MHz RMII Reference Clock Output Does Not Satisfy Clock Input
Requirements of RMII Ethernet PHYs
Revisions Affected
2.1, 2.0, 1.0
Details
The 50-MHz RMII reference clock output is sourced from the ADPLLS CORE PLL which
is not a low-jitter clock source. Therefore, the clock jitter of this output is greater than the
input requirements for most RMII Ethernet PHYs.
Workarounds
Configure the respective RMII reference clock to input mode and use an external low-
jitter LVCMOS clock source or RMII Ethernet PHY with a clock output to source the RMII
reference clock.
RMII1_REFCLK can be configured to input mode by setting bit 6 of the GMII_SEL
register to 1b. RMII2_REFCLK can be configured to input mode by setting bit 7 of the
GMII_SEL register to 1b.
21 SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
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