Usage Notes and Known Design Exceptions to Functional Specifications
Advisory 1.0.17
VDDS_DDR: High-Power Consumption During DeepSleep0
Revisions Affected
1.0
Details
The REG_PHY_ENABLE_DYNAMIC PWRDN bit in the DDR_PHY_CTRL_1 register
provides control for powering down the SSTL and HSTL input buffers to achieve lower
power consumption from the VDDS_DDR power source. This register is reset to its
default value during DeepSleep0 which prevents powering down the DDR SSTL and
HSTL input buffers which causes higher power consumption during DeepSleep0.
Workarounds
Input buffers associated with the bi-directional DDR terminals can be configured to
operate as SSTL and HSTL or LVCMOS inputs. Low-power consumption can be
achieved during DeepSleep0 by configuring the input buffers to operate in LVCMOS
mode and enabling internal pull-downs on each of the bi-directional DDR terminals
before entering DeepSleep0. Power consumption from the VDDS_DDR power source of
this solution is similar to powering down the DDR SSTL and HSTL input buffers.
The DDR PHY can be configured to operate in LVCMOS mode by setting the
MDDR_SEL bit in the DDR_IO_CTRL register to 1b.
The internal pull-downs are configured by writing
0011_1111_1111_0000_0000_00pp_pppp_pppp, where p = previous binary value, to
the DDR_DATA0_IOCTRL and DDR_DATA1_IOCTRL registers.
Advisory 1.0.18
ROM: Ethernet Boot Code Does Not Change Default Direction of RMII1 Reference
Clock When Booting from Ethernet Using RMII
Revisions Affected
1.0
Details
The default direction of the RMII1 reference clock is output mode. This mode of
operation is not supported, as described in
When the SYSBOOT[7:6] boot mode inputs are set to 01b, which selects RMII mode,
the RMII1_REF_CLK terminal is configured to operate in the non-supported output mode
as soon as the ROM code changes the MUXMODE bits of the CONF_RMII1_REF_CLK
register from the default state of GPIO0_29 (111b) to RMII1_REFCLK (000b).
This causes contention on the RMII1 reference clock signal if the ROM code attempts to
boot from RMII since the only RMII mode of operation supported requires the
RMII1_REF_CLK terminal to be driven by an external 50-MHz RMII reference clock
source. Therefore, the ROM code must never be configured such that it attempts to boot
from RMII.
Workarounds
Use MII if Ethernet boot is required.
22
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
