2000 N
Max PLL Lock Time =
m
where N = Pre-Divider Ratio
M = PLL Multiplier
90
TMS320C6748
SPRS590G – JUNE 2009 – REVISED JANUARY 2017
www.ti.com
Submit Documentation Feedback
Product Folder Links:
TMS320C6748
Peripheral Information and Electrical Specifications
Copyright © 2009–2017, Texas Instruments Incorporated
(1)
The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 300 and 600 MHz, but the frequency
going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given
voltage operating point.
Table 6-4. Allowed PLL Operating Conditions (PLL0 and PLL1)
NO.
PARAMETER
Default
Value
MIN
MAX
UNIT
1
PLLRST
: Assertion time during initialization
N/A
1000
N/A
ns
2
Lock time
: The time that the application has to wait for
the PLL to acquire lock before setting PLLEN, after
changing PREDIV, PLLM, or OSCIN
N/A
N/A
(1)
OSCIN
cycles
3
PREDIV
: Pre-divider value
/1
/1
/32
-
4
PLLREF
: PLL input frequency
12
30 (if internal oscillator is used)
50 (if external clock is used)
MHz
5
PLLM
: PLL multiplier values
x20
x4
x32
6
PLLOUT
: PLL output frequency
N/A
300
600
MHz
7
POSTDIV
: Post-divider value
/1
/1
/32
-
6.6.2
Device Clock Generation
PLL0 is controlled by PLL Controller 0 and PLL1 is controlled by PLL Controller 1. PLLC0 and PLLC1
manage the clock ratios, alignment, and gating for the system clocks to the chip. The PLLCs are
responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock
inputs (PLLC0 only), multiply factors within the PLLs, and post-division for each of the chip-level clocks
from the PLLs outputs. PLLC0 also controls reset propagation through the chip, clock alignment, and test
points.
PLLC0 provides clocks for the majority of the system but PLLC1 provides clocks to the DDR2/mDDR
Controller and the ASYNC3 clock domain to provide frequency scaling immunity to a defined set or
peripherals. The ASYNC3 clock domain can either derive its clock from PLL1_SYSCLK2 (for frequency
scaling immunity from PLL0) or from PLL0_SYSCLK2 (for synchronous timing with PLL0) depending on
the application requirements. In addition, some peripherals have specific clock options independent of the
ASYNC clock domain.
6.6.3
Dynamic Voltage and Frequency Scaling (DVFS)
The processor supports multiple operating points by scaling voltage and frequency to minimize power
consumption for a given level of processor performance.
Frequency scaling is achieved by modifying the setting of the PLL controllers’ multipliers, post-dividers
(POSTDIV), and system clock dividers (SYSCLKn). Modification of the POSTDIV and SYSCLK values
does not require relocking the PLL and provides lower latency to switch between operating points, but at
the expense of the frequencies being limited by the integer divide values (only the divide values are
altered the PLL multiplier is left unmodified). Non integer divide frequency values can be achieved by
changing both the multiplier and the divide values, but when the PLL multiplier is changed the PLL must
relock, incurring additional latency to change between operating points. Detailed information on modifying
the PLL Controller settings can be found in the
TMS320C6748 DSP System Reference Guide
(
SPRUGJ7
).
