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TMS320C6748
www.ti.com SPRS590G – JUNE 2009 – REVISED JANUARY 2017
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Peripheral Information and Electrical Specifications
Copyright © 2009–2017, Texas Instruments Incorporated
(1) P = SYSCLK2 period; S = t
c(SPC)S
(SPI slave bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
Table 6-69. General Timing Requirements for SPI0 Slave Modes
(1)
NO.
1.3V, 1.2V 1.1V 1.0V
UNIT
MIN MAX MIN MAX MIN MAX
9 t
c(SPC)S
Cycle Time, SPI0_CLK, All Slave Modes 40
(2)
50
(2)
60
(2)
ns
10 t
w(SPCH)S
Pulse Width High, SPI0_CLK, All Slave Modes 18 22 27 ns
11 t
w(SPCL)S
Pulse Width Low, SPI0_CLK, All Slave Modes 18 22 27 ns
12 t
su(SOMI_SPC)S
Setup time, transmit data
written to SPI before initial
clock edge from
master.
(3) (4)
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P 2P 2P
ns
Polarity = 0, Phase = 1,
to SPI0_CLK rising
2P 2P 2P
Polarity = 1, Phase = 0,
to SPI0_CLK falling
2P 2P 2P
Polarity = 1, Phase = 1,
to SPI0_CLK falling
2P 2P 2P
13 t
d(SPC_SOMI)S
Delay, subsequent bits valid
on SPI0_SOMI after
transmit edge of SPI0_CLK
Polarity = 0, Phase = 0,
from SPI0_CLK rising
17 20 27
ns
Polarity = 0, Phase = 1,
from SPI0_CLK falling
17 20 27
Polarity = 1, Phase = 0,
from SPI0_CLK falling
17 20 27
Polarity = 1, Phase = 1,
from SPI0_CLK rising
17 20 27
14 t
oh(SPC_SOMI)S
Output hold time,
SPI0_SOMI valid after
receive edge of SPI0_CLK
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5S-6 0.5S-16 0.5S-20
ns
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5S-6 0.5S-16 0.5S-20
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5S-6 0.5S-16 0.5S-20
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5S-6 0.5S-16 0.5S-20
15 t
su(SIMO_SPC)S
Input Setup Time,
SPI0_SIMO valid before
receive edge of SPI0_CLK
Polarity = 0, Phase = 0,
to SPI0_CLK falling
1.5 1.5 1.5
ns
Polarity = 0, Phase = 1,
to SPI0_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 0,
to SPI0_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
1.5 1.5 1.5
16 t
ih(SPC_SIMO)S
Input Hold Time,
SPI0_SIMO valid after
receive edge of SPI0_CLK
Polarity = 0, Phase = 0,
from SPI0_CLK falling
4 4 5
ns
Polarity = 0, Phase = 1,
from SPI0_CLK rising
4 4 5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
4 4 5
Polarity = 1, Phase = 1,
from SPI0_CLK falling
4 4 5