MII_TXCLK
2
3
1
MII_RXCLK
2
3
1
200
TMS320C6748
SPRS590G – JUNE 2009 – REVISED JANUARY 2017
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Peripheral Information and Electrical Specifications
Copyright © 2009–2017, Texas Instruments Incorporated
Table 6-97. EMAC Control Module RAM
BYTE ADDRESS
DESCRIPTION
0x01E2 0000 - 0x01E2 1FFF
EMAC Local Buffer Descriptor Memory
6.22.1.1
EMAC Electrical Data/Timing
Table 6-98. Timing Requirements for MII_RXCLK (see
Figure 6-47
)
NO.
1.3V, 1.2V, 1.1V
1.0V
UNIT
10 Mbps
100 Mbps
10 Mbps
MIN
MAX
MIN
MAX
MIN
MAX
1
t
c(MII_RXCLK)
Cycle time, MII_RXCLK
400
40
400
ns
2
t
w(MII_RXCLKH)
Pulse duration, MII_RXCLK high
140
14
140
ns
3
t
w(MII_RXCLKL)
Pulse duration, MII_RXCLK low
140
14
140
ns
Figure 6-47. MII_RXCLK Timing (EMAC - Receive)
Table 6-99. Timing Requirements for MII_TXCLK (see
Figure 6-48
)
NO.
1.3V, 1.2V, 1.1V
1.0V
UNIT
10 Mbps
100 Mbps
10 Mbps
MIN
MAX
MIN
MAX
MIN
MAX
1
t
c(MII_TXCLK)
Cycle time, MII_TXCLK
400
40
400
ns
2
t
w(MII_TXCLKH)
Pulse duration, MII_TXCLK high
140
14
140
ns
3
t
w(MII_TXCLKL)
Pulse duration, MII_TXCLK low
140
14
140
ns
Figure 6-48. MII_TXCLK Timing (EMAC - Transmit)