Texas Instruments LM5066I EVM, Руководство пользователя

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Q1
Z1/C1
R2
R3
To
Load
R
S
CARD EDGE
CONNECTOR
PLUG-IN CARD
V
IN
GND
OUT
PGD
PWR
TIMER
RETRY
SCL
SMBA VREF
DIODE
VAUX
SENSE
GATE
VIN_K
UVLO/EN
OVLO
AGND
SDAI
FB
CL
VDD
ADR0
ADR1
ADR2
LM5066I
VIN
GND
SDAO
MMBT3904
R1
Layout Guidelines
www.ti.com
7 Layout Guidelines
The following guidelines should be followed when designing the PC board for the LM5066I:
1. Place the LM5066I close to the board’s input connector to minimize trace inductance from the
connector to the MOSFET.
2. Place a TVS, Z1, directly adjacent to the VIN and GND pins of the LM5066I to help minimize voltage
transients which may occur on the input supply line. The TVS should be chosen such that the peak
VIN is just lower the TVS reverse-bias voltage. Transients of
≥
20 V over the nominal input voltage can
easily occur when the load current is shut off. A small capacitor may be sufficient for low current sense
applications (I <2 A). TI recommends to test the VIN input voltage transient performance of the circuit
by current limiting or shorting the load and measuring the peak input voltage transient.
3. Place a 1- μ F ceramic capacitor as close as possible to VREF pin.
4. Place a 1- μ F ceramic capacitor as close as possible to VDD pin.
5.
6. The sense resistor (RS) should be placed close to the LM5066I. A trace should connect the VIN pad
and Q1 pad of the sense resistor to VIN_K and SENSE pins, respectively. Connect RS using the
Kelvin techniques shown in
Figure 16 .
7. The high-current path from the board’s input to the load (through Q1), and the return path, should be
parallel and close to each other to minimize loop inductance.
8. The AGND and GND connections should be connected at the pins of the device. The ground
connections for the various components around the LM5066I should be connected directly to each
other and to the LM5066I’s GND and AGND pin connection, and then connected to the system ground
at one point. Do not connect the various component grounds to each other through the high current
ground line.
9. Provide adequate thermal sinking for the series-pass device (Q1) to help reduce stresses during turn-
on and turn-off.
10. The board’s edge connector can be designed such that the LM5066I detects through the UVLO/EN
pin that the board is being removed, and responds by turning off the load before the supply voltage is
disconnected. For example, in
Figure 17 , the voltage at the UVLO/EN pin goes to ground before VIN is
removed from the LM5066I as a result of the shorter edge connector pin. When the board is inserted
into the edge connector, the system voltage is applied to the LM5066I’s VIN pin before the UVLO
voltage is taken high, thereby allowing the LM5066I to turn on the output in a controlled fashion.
Figure 16. Recommended Board Connector Design
18 LM5066IEVM-626 Evaluation Module (EVM) SNVU444 – May 2014
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