Texas Instruments LM5066I EVM, Руководство пользователя

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General Configuration and Description
3 General Configuration and Description
3.1 Physical Access
Table 2 lists the LM5066IEVM-626 connector and functionality, Table 3 describes the test point
availability, and Table 4 describes the switch functionality.
Table 2. Connector Functionality
Connector Label Description
J1 VIN Power bus input. Apply bus input voltage between J1 and J2.
J2 GND Power bus input return connector. Apply bus input voltage between J1 and J2.
J3 VOUT Switched bus output. Apply the load between J3 and J4.
J4 GND Switch bus output return connector. Apply the load between J3 and J4.
J5 PMBus interface
Table 3. Test Points
Test Point Label Description
TP1 VIN Positive supply input
TP2 VINK Positive supply Kelvin sense pin on sense resistor
TP3 SENSEK Sense Kelvin sense pin on sense resistor
TP4 SENSEK Sense pin test point
TP5 GATE Gate drive output
TP6 VOUT_S Output voltage at the pass FET
TP7 VOUT Output voltage at the load
TP8 FB Power Good feedback
TP9 PG Power Good indicator
TP10 TIMER Timing capacitor voltage
TP11 VREF Internal reference voltage
TP12 VAUX Auxiliary ADC input
TP13 EN UVLO/EN pin voltage
TP14 OVLO OVLO pin voltage
TP15, TP19, TP20, TP21 GND Circuit ground
TP16 SDA SMBus input/output
TP17 SCL SMBis clock
TP18 SMBA SMBUS alert line (active low)
TP22 VDD Internal sub-regulator 4.85-V output
TP23 RETRYB Fault retry input
TP24 CL Current limit range
TP25 ADR0 SMBus address line 0
TP26 ADR1 SMBus address line 1
TP27 ADR2 SMBus address line 2
5 SNVU444 – May 2014 LM5066IEVM-626 Evaluation Module (EVM)
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