EVM Dual BoC
BoC - Quick Start Guide
Revision 0.4 – preliminary
Page
2 of 31
a.
PCIeREFCLK Crystal-to-HCSL Output Enable Header [25] ....................................................................... 17
b.
PCIeREFCLK Logic ...................................................................................................................................... 18
c.
Alternate PCIeREFCLK Inputs [4] ................................................................................................................ 18
XVII.
RP1FB Source [7].......................................................................................................................................... 18
XVIII.
RADSYNC & PHYSYNC Triggering [6] ........................................................................................................ 18
XIX.
Warnings and Cautions .................................................................................................................................. 20
XX.
Pin Assignment [Board A] ............................................................................................................................. 20
XXI.
Pin Assignment [Board B] ............................................................................................................................. 22
XXII.
Header Intra-Connections ............................................................................................................................. 24
Table of Figures
Figure 1 - BoC Top View ............................................................................................................................................... 3
Figure 2: Front View, Assembled BoC .......................................................................................................................... 4
Figure 3 - Block Diagram .............................................................................................................................................. 5
Figure 4 - BoC Logic Power Source Selection .............................................................................................................. 6
Figure 5: BoC Power Supply ......................................................................................................................................... 7
Figure 6 - I2C Programming Header ............................................................................................................................ 9
Figure 7: REFCLK Logic ............................................................................................................................................ 11
Figure 8: REFCLK Biasing Components .................................................................................................................... 11
Figure 9: RP1CLK Logic ............................................................................................................................................. 13
Figure 10: RP1CLK Biasing Components ................................................................................................................... 14
Figure 11: TCLK_B Interface ...................................................................................................................................... 15
Figure 12: TCLK_B Logic ........................................................................................................................................... 16
Figure 13: TCLK_B Biasing Components ................................................................................................................... 16
Figure 14: TCLK_B Interface ...................................................................................................................................... 17
Figure 15: RP1CLK Logic ........................................................................................................................................... 18
Figure 16: RADSYNC & PHYSYNC Control .............................................................................................................. 19
Figure 17: Cross Triggering Switch ............................................................................................................................ 19
Table of Tables
Table 1: Factory Configuration ..................................................................................................................................... 6
Table 2: JP5 & JP4 (Board A & B) I2C Switch Configuration ................................................................................... 10
Table 3: JP10 REFCLK Enable Header ...................................................................................................................... 10
Table 4: JP1 RP1CLK Enable Header ........................................................................................................................ 13
Table 5: JP2 TCLK_B Enable Header ........................................................................................................................ 15
Table 6: JP3 PCIEREFCLK Enable Header ............................................................................................................... 17
Table 7: RADSYNC / PHYSYNC Trigger Configuration ............................................................................................. 20
Table 8: AMC B+ Header Pin Assignment – Board A ................................................................................................ 20
Table 9: AMC B+ Header Pin Assignment – Board B ................................................................................................ 22
Table 10: SerDes Board2Board Connections .............................................................................................................. 24