EVM Dual BoC
Revision 0.4 – preliminary
BoC - Quick Start Guide
Page 19 of
31
1
Board B RADSYNC (Output)
Board B PHYSYNC (Output)
Board A PHYSYNC (Output)
Board A RADSYNC (Output)
Board A Timer0 (Input)
Board B Timer0 (Input)
4
2
3
J5
6
5
12
9
11
10
7
8
ON
Figure 16: RADSYNC & PHYSYNC Control
The following figure illustrates the logic implemented to support this cross triggering.
Figure 17: Cross Triggering Switch
JP7
HDR_1x1
1
R67
0
Placement of JP6/JP8 should be identical to JP7/JP9.
-Placement of R67 should be identical in distance to
R68 from Headers and switch
R68
0
FACTORY J9 SETTINGS
01 - 12 Board B RADSYNC - ON
02 - 11 Board B PHYSYNC - ON
03 - 01 Board A RADSYNC - OFF
04 - 09 Board A PHYSYNC - OFF
05 - 08 TimerOut 0 Board B - ON
06 - 07 TimerOut 0 Board A - OFF
ON
J5
SDA06H1SBD
1
2
3
4
5
6
7
8
9
1
0
1
2
1
1
JP8
HDR_1x1
1
JP9
HDR_1x1
1
OUT
B_TIMEROUT_0
4
IN
B_TIMERIN_0
4
JP6
HDR_1x1
1
IN
A_TIMEROUT_0 3
OUT
A_TIMERIN_0 3
OUT
B_PHY SY NC
4
OUT
B_RADSY NC
4
OUT
A_PHY SY NC 3
OUT
A_RADSY NC 3