EVM Dual BoC
Revision 0.4 – preliminary
BoC - Quick Start Guide
Page 15 of
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30.72MHz to both EVM’s for TCLK_B. By default the shunt is installed and the REFCLK
source is disabled.
Table 5: JP2 TCLK_B Enable Header
JP2
ON
Disabled
OFF
Enabled
OFF
ON
1
X
2
X
b. TCLK_B Signal Outputs [2, 13]
There are two headers provided on your BoC; J1 & J2. Board A makes use of the 1 x 4
header whereas Board A interfaces with J2. In some current production TI EVM’s these
pins are connected to the AMC headers, others not – confirm proper connection before
powering up or using this feature. Due to layout constrainst J1 and J2 pinouts are not
identical – please refer to the following figure and the silk screen on your BoC for proper
pin locations.
J2
1
TCLKA_P
TCLKA_N
TCLKB_P
TCLKB_N
4
2
3
J1
1
TCLKA_P
TCLKA_N
TCLKB_N
TCLKB_P
4
2
3
Figure 11: TCLK_B Interface
The oscillator source (U5) is routed into the low jitter 1:2 clock buffer (U6), the output is a
biased LVPECL (low voltage PECL). Some EVM input logic levels may have to be
adjusted to properly interface with your DSP, consult your DSP data manual and the data
manual for the CDCLVP1102 before using this hardware or making any modifications.
Prior to proceeding it will also be necessary to confirm that the TCLK_B pins are not
assigned other functions and that no contention will occur. Your BoC REFCLKp/n outputs
are
not
AC coupled, however they are biased. The current biasing scheme implemented
is designed to provide the appropriate swing for most TI DSP’s available today.
CAUTION
: Different versions of EVM’s have different pinout configurations,
confirm that your EVM supports this interface and feature.