EVM Dual BoC
Revision 0.4 – preliminary
BoC - Quick Start Guide
Page 17 of
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J2
1
TCLKA_P
TCLKA_N
TCLKB_P
TCLKB_N
4
2
3
J1
1
TCLKA_P
TCLKA_N
TCLKB_N
TCLKB_P
4
2
3
Figure 14: TCLK_B Interface
Before using this interface to your BoC, confirm the logic levels and terminations are
correct.
XVI.
Common PCIeREFCLK Source [25]
Your BoC has the capability of supplying a common PCIeREFCLK to both EVM’s. This
common PCIeREFCLK is generated on the BoC and sourced from a dedicated 25MHz
crystal (U8) connected to a low noise crystal-to-HCSL clock generator (U7). On your BoC
is JP3, this header and shunt are used to enable or disable the differential oscillator on
the BoC. By default the shunt is applied on this header and the output disabled.
Not all EVM’s directly support this feature, future EVM’s will incorporate this feature to
allow for improved functionality and testing. The clock routing is skew matched between
AMC headers to within 5ps.
a. PCIeREFCLK Crystal-to-HCSL Output Enable Header [25]
The following table defines the possible configurations for JP3. JP3 is used to enable or
disable the 25.00MHz differential output connected to each respective AMC header. By
default the shunt is installed and the PCIEREFCLK output is disabled.
Table 6: JP3 PCIEREFCLK Enable Header
JP3
ON
Disabled
OFF
Enabled
OFF
ON
1
X
2
X
CAUTION
: Different versions of EVM’s have different pinout configurations,
confirm that your EVM supports this interface and feature.