Texas Instruments CI2EVM BoC Скачать руководство пользователя страница 2

5

5

4

4

3

3

2

2

1

1

D

D

C

C

B

B

A

A

Board A
SGMII [1]

TDO Output from Brd A to Brd B

Board A
JTAG Interface

Board A
Clocks

Board A
SGMII [0]

Board A
RP1CLK

Board A
AIF[0:5]

Board A
AIF CLK & FS

Board A
Expansion I2C

Board A
SRIO[1:4]

Board A
PCIe[4:7]

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

FROM EVM A

TO EVM A

TO EVM A

TO EVM A

TO EVM A

TO EVM A

CONNECTOR REFLECTS BACKPLANE PIN OUTS

TDI
TDO_2_TDI
TRST#
TMS
TCK

A_AMC0_SGMII1_TX_DP
A_AMC0_SGMII1_TX_DN

A_AMC0_SGMII1_RX_DP
A_AMC0_SGMII1_RX_DN

A_DSP_RP1CLKN

A_DSP_RP1CLKP

A_AMCC_P7_PCIe_RX2P
A_AMCC_P7_PCIe_RX2N

A_AMCC_P6_PCIe_RX1P
A_AMCC_P6_PCIe_RX1N

A_AMCC_P7_PCIe_TX2P
A_AMCC_P7_PCIe_TX2N

A_AMCC_P6_PCIe_TX1P
A_AMCC_P6_PCIe_TX1N

A_AMCC_P13_AIF1_RXN

A_AMCC_P13_AIF1_RXP

A_AMCC_P13_AIF1_TXP
A_AMCC_P13_AIF1_TXN

A_AMCC_P14_AIF2_RXP
A_AMCC_P14_AIF2_RXN

A_AMCC_P14_AIF2_TXP
A_AMCC_P14_AIF2_TXN

A_AMCC_P15_AIF3_RXP
A_AMCC_P15_AIF3_RXN

A_AMCC_P15_AIF3_TXP
A_AMCC_P15_AIF3_TXN

A_AMCC_P12_AIF0_RXN

A_AMCC_P12_AIF0_RXP

A_AMCC_P12_AIF0_TXP
A_AMCC_P12_AIF0_TXN

A_AMCC_P17_AIF4_RXP
A_AMCC_P17_AIF4_RXN

A_AMCC_P17_AIF4_TXP
A_AMCC_P17_AIF4_TXN

A_AMCC_P18_AIF5_RXP
A_AMCC_P18_AIF5_RXN

A_AMCC_P18_AIF5_TXP
A_AMCC_P18_AIF5_TXN

A_AMC0_SGMII0_TX_DP
A_AMC0_SGMII0_TX_DN

A_AMCC_P11_SRIO4_RXN

A_AMCC_P11_SRIO4_RXP

A_AMCC_P9_SRIO2_TXN

A_AMCC_P9_SRIO2_TXP

A_AMCC_P10_SRIO3_RXP
A_AMCC_P10_SRIO3_RXN

A_AMCC_P8_SRIO1_TXN

A_AMCC_P8_SRIO1_TXP

A_AMCC_P9_SRIO2_RXP
A_AMCC_P9_SRIO2_RXN

A_AMCC_P11_SRIO4_TXP
A_AMCC_P11_SRIO4_TXN

A_AMCC_P8_SRIO1_RXP
A_AMCC_P8_SRIO1_RXN

A_AMCC_P10_SRIO3_TXP
A_AMCC_P10_SRIO3_TXN

A_PCIE_REF_CLK_P

A_AMC0_SGMII0_RX_DP
A_AMC0_SGMII0_RX_DN

A_PCIE_REF_CLK_N

A_AMCC_P5_PCIe_RX2P
A_AMCC_P5_PCIe_RX2N

A_AMCC_P4_PCIe_RX1P
A_AMCC_P4_PCIe_RX1N

A_AMCC_P5_PCIe_TX2P
A_AMCC_P5_PCIe_TX2N

A_AMCC_P4_PCIe_TX1P
A_AMCC_P4_PCIe_TX1N

A_TCLKA_P
A_TCLKA_N

A_TCLKB_P
A_TCLKB_N

A_REFCLK_P
A_REFCLK_N

A_TIMEROUT_0
A_TIMERIN_0

A_RP1FBP
A_RP1FBN

A_DSP_SDA_AMC

A_DSP_SCL_AMC

A_PHYSYNC
A_RADSYNC

A_VCC12

IN

B_AMC0_SGMII1_TX_DP

4

IN

B_AMC0_SGMII1_TX_DN

4

OUT

A_AMC0_SGMII1_TX_DP

4

OUT

A_AMC0_SGMII1_TX_DN

4

IN

TDI 7

OUT

TDO_2_TDI 4

IN

TRST# 4,7

IN

TMS 4,7

IN

A_TCK 7

IN

A_DSP_RP1CLKN 5

IN

A_DSP_RP1CLKP 5

OUT

A_AMCC_P6_PCIe_TX1P

4

OUT

A_AMCC_P6_PCIe_TX1N

4

IN

B_AMCC_P6_PCIe_TX1P

4

IN

B_AMCC_P6_PCIe_TX1N

4

IN

B_AMCC_P7_PCIe_TX2P

4

IN

B_AMCC_P7_PCIe_TX2N

4

OUT

A_AMCC_P7_PCIe_TX2P

4

OUT

A_AMCC_P7_PCIe_TX2N

4

IN

B_AMC0_SGMII0_TX_DP

4

IN

B_AMC0_SGMII0_TX_DN

4

OUT

A_AMC0_SGMII0_TX_DP

4

OUT

A_AMC0_SGMII0_TX_DN

4

OUT

A_AMCC_P4_PCIe_TX1P

4

OUT

A_AMCC_P4_PCIe_TX1N

4

IN

B_AMCC_P4_PCIe_TX1P

4

IN

B_AMCC_P4_PCIe_TX1N

4

IN

B_AMCC_P5_PCIe_TX2P

4

IN

B_AMCC_P5_PCIe_TX2N

4

OUT

A_AMCC_P5_PCIe_TX2P

4

OUT

A_AMCC_P5_PCIe_TX2N

4

IN

A_TCLKA_P

5

IN

A_TCLKA_N

5

IN

A_TCLKB_P

5

IN

A_TCLKB_N

5

IN

A_PCIE_REF_CLK_P

5

IN

A_PCIE_REF_CLK_N

5

IN

A_RP1FBN 6

IN

A_RP1FBP 6

IN

A_RADSYNC

6

IN

A_PHYSYNC

6

IN

B_AMCC_P18_AIF5_TXN 4

IN

B_AMCC_P18_AIF5_TXP 4

OUT

A_AMCC_P17_AIF4_TXP 4

OUT

A_AMCC_P17_AIF4_TXN 4

IN

B_AMCC_P17_AIF4_TXN 4

IN

B_AMCC_P17_AIF4_TXP 4

OUT

A_AMCC_P18_AIF5_TXP 4

OUT

A_AMCC_P18_AIF5_TXN 4

OUT

A_AMCC_P15_AIF3_TXP 4

OUT

A_AMCC_P15_AIF3_TXN 4

OUT

A_AMCC_P14_AIF2_TXP 4

OUT

A_AMCC_P14_AIF2_TXN 4

IN

B_AMCC_P15_AIF3_TXN 4

IN

B_AMCC_P15_AIF3_TXP 4

OUT

A_AMCC_P13_AIF1_TXP 4

OUT

A_AMCC_P13_AIF1_TXN 4

IN

B_AMCC_P14_AIF2_TXN 4

IN

B_AMCC_P14_AIF2_TXP 4

OUT

A_AMCC_P12_AIF0_TXP 4

OUT

A_AMCC_P12_AIF0_TXN 4

IN

B_AMCC_P13_AIF1_TXN 4

IN

B_AMCC_P13_AIF1_TXP 4

IN

B_AMCC_P12_AIF0_TXN 4

IN

B_AMCC_P12_AIF0_TXP 4

OUT

A_AMCC_P11_SRIO4_TXP 4

OUT

A_AMCC_P11_SRIO4_TXN 4

IN

B_AMCC_P11_SRIO4_TXP 4

IN

B_AMCC_P11_SRIO4_TXN 4

OUT

A_AMCC_P10_SRIO3_TXP 4

OUT

A_AMCC_P10_SRIO3_TXN 4

IN

B_AMCC_P10_SRIO3_TXP 4

IN

B_AMCC_P10_SRIO3_TXN 4

OUT

A_AMCC_P9_SRIO2_TXP 4

OUT

A_AMCC_P9_SRIO2_TXN 4

IN

B_AMCC_P9_SRIO2_TXP 4

IN

B_AMCC_P9_SRIO2_TXN 4

OUT

A_AMCC_P8_SRIO1_TXP 4

OUT

A_AMCC_P8_SRIO1_TXN 4

IN

B_AMCC_P8_SRIO1_TXP 4

IN

B_AMCC_P8_SRIO1_TXN 4

BI

A_AMC_EXP_SDA 6

OUT

A_TIMERIN_0 6

IN

A_AMC_EXP_SCL 6

IN

A_TIMEROUT_0 6

IN

A_REFCLK_N 7

IN

A_REFCLK_P 7

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

E

LC_2-EVM_BoC-0002 - Board B Interface

B

3

10

Friday, September 09, 2011

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

E

LC_2-EVM_BoC-0002 - Board B Interface

B

3

10

Friday, September 09, 2011

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

E

LC_2-EVM_BoC-0002 - Board B Interface

B

3

10

Friday, September 09, 2011

R3

DNI

R4

DNI

R5

0

R6

0

A1

AMC_BACKPLANE_CONNECTOR

<Characteristic>

GND_1

1

GND_2

7

GND_3

10

PWR_12V_1

2

PS1

3

MP

4

GA0

5

RSRVD6

6

RSRVD8

8

PWR_12V_2

9

Rx0+

11

Rx0-

12

GND_4

13

Tx0+

14

Tx0-

15

GND_5

16

GA1

17

PWR_12V_3

18

GND_6

19

Rx1+

20

Rx1-

21

GND_7

22

Tx1+

23

Tx1-

24

GND_8

25

GA2

26

PWR_12V_4

27

GND_9

28

Rx2+

29

Rx2-

30

GND_10

31

Tx2+

32

Tx2-

33

GND_11

34

Rx3+

35

Rx3-

36

GND_12

37

Tx3+

38

Tx3-

39

GND_13

40

ENABLE

41

PWR_12V_5

42

GND_14

43

Rx4+

44

Rx4-

45

GND_15

46

Tx4+

47

Tx4-

48

GND_16

49

Rx5+

50

Rx5-

51

GND_17

52

Tx5+

53

Tx5-

54

GND_18

55

SCL_L

56

GND_19

58

Rx6+

59

Rx6-

60

GND_20

61

Tx6+

62

Tx6-

63

GND_21

64

Rx7+

65

Rx7-

66

GND_22

67

Tx7+

68

Tx7-

69

GND_23

70

SDA_L

71

PWR_12V_6

57

PWR_12V_7

72

GND_24

73

TCLKA+

74

TCLKA-

75

GND_25

76

TCLKB+

77

TCLKB-

78

GND_26

79

FCLKA+

80

FCLKA-

81

GND_27

82

PS0

83

PWR_12V_8

84

GND_28

85

GND_29

86

Tx8-

87

Tx8+

88

Rx8+

91

Rx8-

90

GND_30

89

Tx9+

94

Tx9-

93

GND_31

92

Rx9+

97

Rx9-

96

GND_32

95

Tx10+

100

Tx10-

99

GND_33

98

Rx10+

103

Rx10-

102

GND_34

101

Tx11+

106

Tx11-

105

GND_35

104

Rx11+

109

Rx11-

108

GND_36

107

Tx12+

112

Tx12-

111

GND_37

110

Rx12+

115

Rx12-

114

GND_38

113

Tx13+

118

Tx13-

117

GND_39

116

Rx13+

121

Rx13-

120

GND_40

119

Tx14+

124

Tx14-

123

GND_41

122

Rx14+

127

Rx14-

126

GND_42

125

GND_43

128

Tx15+

130

Tx15-

129

GND_44

131

Rx15-

132

Rx15+

133

GND_45

134

TCLKC+

136

TCLKC-

135

TCLKD+

139

TCLKD-

138

GND_46

137

Tx17+

142

Tx17-

141

GND_47

140

Rx17+

145

Rx17-

144

GND_48

143

Rx18+

151

Rx18-

150

GND_50

149

Tx18+

148

Tx18-

147

GND_49

146

Rx19+

157

Rx19-

156

GND_52

155

Tx19+

154

Tx19-

153

GND_51

152

Rx20+

163

Rx20-

162

GND_54

161

Tx20+

160

Tx20-

159

GND_53

158

GND_55

164

TCK

165

TMS

166

TRST

167

TDO

168

TDI

169

GND_56

170

R1

0

R2

0

Содержание CI2EVM BoC

Страница 1: ...cription 3 II Hardware Configuration 6 I Initial Installation Procedure 6 II Default Jumper and Pin Settings 6 III BoC Logic Power Source Selection 20 6 IV EVM Power Source 16 17 18 7 V Emulation Inte...

Страница 2: ...P 5 IN A_TCLKB_N 5 IN A_PCIE_REF_CLK_P 5 IN A_PCIE_REF_CLK_N 5 IN A_ IN A_ IN A_ IN A_ IN B_AMCC_P18_AIF5_TXN 4 IN B_AMCC_P18_AIF5_TXP 4 OUT A_AMCC_P17_AIF4_TXP 4 OUT A_AMCC_P17_AIF4_TXN 4 IN B_AMCC_P...

Страница 3: ...5_PCIe_TX2N 3 IN A_AMCC_P4_PCIe_TX1P 3 IN A_AMCC_P4_PCIe_TX1N 3 IN B_PCIE_REF_CLK_P 5 IN B_PCIE_REF_CLK_N 5 IN B_TCLKA_P 5 IN B_TCLKA_N 5 IN B_TCLKB_P 5 IN B_TCLKB_N 5 IN A_AMCC_P18_AIF5 IN A_AMCC_P18...

Страница 4: ...XO LC By default leave Disabled RPICLKP N nets to be matched length fro R37 40 42 49 must be placed close to o Pay attention to mounting require BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3...

Страница 5: ...istor junctions to AMC headers must be identical Placement of JP6 JP8 should be identical to JP7 JP9 Placement of R67 should be identical in distance to R68 from Headers and switch BRD3V3 BRD3V3 BRD3V...

Страница 6: ...LK_N 4 Title Size Date B Title Size Date B Title Size Date B R82 150 BJ_MH1 Banana 2142 1 1 F1 Fuse 0154001 01 1 2 2 MH3 Mounting_Hole 1 1 R79 75 R83 150 R74 DNI BJ_MH2 Banana 2142 1 1 C18 0 1 F F2 Fu...

Страница 7: ...7 REFCLK Logic 11 Figure 8 REFCLK Biasing Components 11 Figure 9 RP1CLK Logic 13 Figure 10 RP1CLK Biasing Components 14 Figure 11 TCLK_B Interface 15 Figure 12 TCLK_B Logic 16 Figure 13 TCLK_B Biasin...

Страница 8: ...on Interface J7 2 Board B TCKA B Header J1 3 Board B AMC B EVM Interface Connector 4 Auxilluary PCIe Clock Input SMA Connectors CON3 CON4 5 Board A EEPROM Address Configuration Switch J4 6 Timer Sync...

Страница 9: ...na Jack BJ MH1 19 Board A B REFCLK Source Input Clock Oscillator Enable Control JP10 20 Primary BoC Power Selection Switch J6 21 Board A AMC B EVM Interface Connector 22 Board B Timer0 Output Interfac...

Страница 10: ...LK SRIO TX Lane 4 1 SRIO RX Lane 4 1 TIMERIN_0 TIMEROUT_0 PHYSYNC RADSYNC REFCLKP N RP1FBP N RPICLK P N SGMII RX Lane 1 0 SGMII TX Lane 1 0 PCIe RX Lane 3 0 PCIe TX Lane 3 0 TCLK A P N TCLK B P N PCIe...

Страница 11: ...Switch 0x111110 J6 20 1X3 Header Shunt Installed 1 2 JP1 8 1X2 Header Shunt Installed JP2 14 1X2 Header Shunt Installed JP3 25 1X2 Header Shunt Installed JP4 9 1X2 Header N A JP5 11 1X2 Header N A JP...

Страница 12: ...tured by Pomona part numbers 1581 2 Red 2 required 17 18 1581 0 Black 1 required 16 The mounting pads on the BoC are electrically conductive Due to the height limitations and the need to clear any sup...

Страница 13: ...acitors on your BoC it is assume that your EVM hardware has been properly designed and contains the appropriate AC coupling capacitors on the respective AC nets VII PCIE Interface Your BoC in designed...

Страница 14: ...us for each EVM Each EEPROM is isolated from the other and resides on the AMCC backplane bus to the respective EVM From the factory this interface to each respective EVM is electrically ready for use...

Страница 15: ...cillator Enable Header 19 The following table defines the possible configurations for JP10 JP10 is used to enable or disable the 30 72MHz differential clock source U14 input to the CDCLVP1102 which is...

Страница 16: ...NO STUBS BRD3V3 JP10 HDR_1x2 1 2 R76 10K 0 100 Header 1 shunt needed J5 Default is Not Installed 0 Power Down Hi Z 1 Normal Active Output R75 75 R69 27 R77 75 R78 75 BRD3V3 C12 0 01 F R79 75 R70 150 R...

Страница 17: ...oard B and header JP7 24 is connected to Board A This timer input pin to each respective DSP is provided for convience in the event future connection is required XIV Common RP1CLK Source Your BoC has...

Страница 18: ...5 INP 6 INN 7 Vacref 8 OUTP0 9 OUTN0 10 OUTP1 11 OUTN1 12 NC3 13 NC4 14 NC5 15 Gnd1 16 GP 17 JP1 Default Settings Install shunt between 1 2 Oscillator output is Hi Z Zero stub between CON1 CON2 SMA a...

Страница 19: ...e Not all EVM s directly support this feature future EVM s will incorporate this feature to allow for advanced clocking and test The clock routing is skew matched between AMC headers to within 5ps a T...

Страница 20: ...ons J2 1 TCLKA_P TCLKA_N TCLKB_P TCLKB_N 4 2 3 J1 1 TCLKA_P TCLKA_N TCLKB_N TCLKB_P 4 2 3 Figure 11 TCLK_B Interface The oscillator source U5 is routed into the low jitter 1 2 clock buffer U6 the outp...

Страница 21: ...R33 27 JP2 HDR_1x2 1 2 R36 R41 are 0 ohm 0402 resistors May need to be changed to 0 01uF Capacitors to AC couple U6 Output is LVPECL Resistors R42 R45 have been configured for CML output C10 0 1 F C8...

Страница 22: ...differential oscillator on the BoC By default the shunt is applied on this header and the output disabled Not all EVM s directly support this feature future EVM s will incorporate this feature to all...

Страница 23: ...other making use of the PHYSYNC or RADSYNC pins On future EVM s the timer pins will be routed to the AMC backplane interface until this is implemented the trigger event must be rerouted to the switch...

Страница 24: ...s Triggering Switch JP7 HDR_1x1 1 R67 0 Placement of JP6 JP8 should be identical to JP7 JP9 Placement of R67 should be identical in distance to R68 from Headers and switch R68 0 FACTORYJ9 SETTINGS 01...

Страница 25: ...gs and cautions must be followed to ensure proper operation XX Pin Assignment Board A The following table is provided relative to the AMC piout assignment for your BoC card Table 8 AMC B Header Pin As...

Страница 26: ...Board A 41 N C Board A 130 AIF3_RXp Board A 42 12V Power Board A 129 AIF3_RXn Board A 43 GND Board A 128 GND Board A 44 PCIe4_TXp Board A 127 AIF2_TXp Board A 45 PCIe4_TXn Board A 126 AIF2_TXn Board A...

Страница 27: ...eader Pin Number Signal Header Pin Number Signal Board B 1 GND Board B 170 GND Board B 2 12V Power Board B 169 TDO_2_TDI Board B 3 N C Board B 168 TDO Board B 4 N C Board B 167 TRST Board B 5 N C Boar...

Страница 28: ...Board B 52 GND Board B 119 GND Board B 53 PCIe5_RXp Board B 118 AIF1_RXp Board B 54 PCIe5_RXn Board B 117 AIF1_RXn Board B 55 GND Board B 116 GND Board B 56 N C Board B 115 AIF0_TXp Board B 57 12V Pow...

Страница 29: ...Xp Board B 23 SGMII1_RXp Board A 21 SGMII1_TXn Board B 24 SGMII1_RXn Board A 23 SGMII1_RXp Board B 20 SGMII1_TXp Board A 24 SGMII1_RXn Board B 21 SGMII1_TXn Board Signal Board Signal Board A 44 PCIe4_...

Страница 30: ...Board B 123 AIF2_RXn Board A 124 AIF2_RXp Board B 127 AIF2_TXp Board A 123 AIF2_RXn Board B 126 AIF2_TXn Board A 121 AIF1_TXp Board B 118 AIF1_RXp Board A 120 AIF1_TXn Board B 117 AIF1_RXn Board A 11...

Страница 31: ...al Board A 96 SRIO2_TXn Board B 93 SRIO2_RXn Board A 94 SRIO2_RXp Board B 97 SRIO2_TXp Board A 93 SRIO2_RXn Board B 96 SRIO2_TXn Board A 91 SRIO1_TXp Board B 88 SRIO1_RXp Board A 90 SRIO1_TXn Board B...

Страница 32: ...P 5 IN A_TCLKB_N 5 IN A_PCIE_REF_CLK_P 5 IN A_PCIE_REF_CLK_N 5 IN A_ IN A_ IN A_ IN A_ IN B_AMCC_P18_AIF5_TXN 4 IN B_AMCC_P18_AIF5_TXP 4 OUT A_AMCC_P17_AIF4_TXP 4 OUT A_AMCC_P17_AIF4_TXN 4 IN B_AMCC_P...

Страница 33: ...5_PCIe_TX2N 3 IN A_AMCC_P4_PCIe_TX1P 3 IN A_AMCC_P4_PCIe_TX1N 3 IN B_PCIE_REF_CLK_P 5 IN B_PCIE_REF_CLK_N 5 IN B_TCLKA_P 5 IN B_TCLKA_N 5 IN B_TCLKB_P 5 IN B_TCLKB_N 5 IN A_AMCC_P18_AIF5 IN A_AMCC_P18...

Страница 34: ...XO LC By default leave Disabled RPICLKP N nets to be matched length fro R37 40 42 49 must be placed close to o Pay attention to mounting require BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3...

Страница 35: ...istor junctions to AMC headers must be identical Placement of JP6 JP8 should be identical to JP7 JP9 Placement of R67 should be identical in distance to R68 from Headers and switch BRD3V3 BRD3V3 BRD3V...

Страница 36: ...LK_N 4 Title Size Date B Title Size Date B Title Size Date B R82 150 BJ_MH1 Banana 2142 1 1 F1 Fuse 0154001 01 1 2 2 MH3 Mounting_Hole 1 1 R79 75 R83 150 R74 DNI BJ_MH2 Banana 2142 1 1 C18 0 1 F F2 Fu...

Страница 37: ...118777 HMC723LP3E MAX9979EVKIT MAX5432EVKIT MAX3397EEVKIT MAX14611EVKIT MAX4951AEEVKIT MAX9647EVKIT MAX9684EVKIT MAX4952AEVKIT MAX13035EEVKIT DS1964SEVKIT ESD EVM 001 EVAL CN0414 ARDZ K2 LTCC WBZ K1 D...

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