EVM Dual BoC
Revision 0.4 – preliminary
BoC - Quick Start Guide
Page 9 of
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VIII.
SRIO (Serial RapidIO) Interface
Your BoC in designed to support four (4) lanes of SRIO. The SRIO interface is connected
between each board (A & B) in a manner that provides intercommunication. Board A
transmit (TX) lanes 11:8 are routed to the receive (RX) lanes 11:8 of Board B, and Board
A receive (RX) lanes 11:8 are routed to the transmit (TX) lanes 11:8 of Board B. There
are no AC coupling capacitors on your BoC, it is assume that your EVM hardware has
been properly designed and contains the appropriate AC coupling capacitors on the
respective AC nets.
IX.
AIF (Antenna Interface) Interface
Your BoC in designed to support six (6) lanes of AIF. The AIF interface is connected
between each board (A & B) in a manner that provides intercommunication. Board A
transmit (TX) lanes 18:17 & 15:12 are routed to the receive (RX) lanes 18:17 & 15:12 of
Board B, and Board A receive (RX) lanes 18:17 & 15:12 are routed to the transmit (TX)
lanes 18:17 & 15:12 of Board B. There are no AC coupling capacitors on your BoC, it is
assume that your EVM hardware has been properly designed and contains the
appropriate AC coupling capacitors on the respective AC nets.
X.
I2C interface [5, 9, 11, 23]
Your BoC card is designed with EEPROMs sitting on the I2C bus for each EVM. Each
EEPROM is isolated from the other and resides on the AMCC backplane bus to the
respective EVM. From the factory, this interface to each respective EVM is electrically
ready for use but not directly connected to the EVM’s. Prior to use, the series termination
resistors (0ohm) are required to be installed. These resistors are designed in as SMT
components, 0402 in size. The following figure illustrates the pin out for both EEPROM
interface headers. These headers (JP4 & JP5) can be used to program the individual on
board EEPROMs. Your EEPROMS are blank from Texas Instruments. JP5 is the
interface and programming header for Board A, and JP4 is the interface and
programming header for Board B.
1
2
[Pin 1] SCL
[Pin 2] SDA
Figure 6 - I2C Programming Header
Each EEPROM contains a dedicated switch used to define the address. This feature was
added to allow the end user the ability to change the EEPROM address in the event there
was address contention do to something else sitting on the same bus. An on indication is
denoted as “0”. JP4 is default configured as 0x011, JP5 is default configured as 0x000.
The following table is provided to illustrate the switch to eeprom address correlation.
CAUTION
: Confirm that your EVM supports this interface and that the
number of interfaces as well as the pinout locations is supported correctly.
CAUTION
: Confirm that your EVM supports this interface and that the
number of interfaces as well as the pinout locations is supported correctly.