Overview
A versatile five-channel DMA controller (
) is available in the system, accesses memory using
the XDATA memory space, and thus has access to all physical memories. Each channel (trigger, priority,
transfer mode, addressing mode, source and destination pointers, and transfer count) is configured with
DMA descriptors anywhere in memory. Many of the hardware peripherals (AES core, flash controller,
USARTs, timers, ADC interface) achieve highly efficient operation by using the DMA controller for data
transfers between SFR or XREG addresses and flash/SRAM.
Timer 1 (
) is a 16-bit timer with timer/counter/PWM functionality. It has a programmable
prescaler, a 16-bit period value, and five individually programmable counter/capture channels, each with a
16-bit compare value. Each of the counter/capture channels can be used as a PWM output or to capture
the timing of edges on input signals. It can also be configured in IR generation mode, where it counts
Timer 3 periods and the output is ANDed with the output of Timer 3 to generate modulated consumer IR
signals with minimal CPU interaction (see
).
Timer 2 (MAC Timer) (
) is specially designed for supporting an IEEE 802.15.4 MAC or other
time-slotted protocol in software. The timer has a configurable timer period and a 24-bit overflow counter
that can be used to keep track of the number of periods that have transpired. A 40-bit capture register is
also used to record the exact time at which a start-of-frame delimiter is received/transmitted or the exact
time at which transmission ends, as well as two 16-bit output compare registers and two 24-bit overflow
compare registers that can send various command strobes (start RX, start TX, etc.) at specific times to the
radio modules.
Timer 3 and Timer 4 (
) are 8-bit timers with timer/counter/PWM functionality. They have a
programmable prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit
compare value. Each of the counter channels can be used as a PWM output.
The Sleep Timer (
) is an ultralow-power timer that counts 32-kHz crystal oscillator or 32-kHz
RC oscillator periods. The Sleep Timer runs continuously in all operating modes except power mode 3
(PM3). Typical applications of this timer are as a real-time counter or as a wake-up timer for coming out of
power mode 1 (PM1) or power mode 2 (PM2).
The ADC (
) supports 7 bits (30 kHz bandwidth) to 12 bits (4 kHz bandwidth) of resolution. DC
and audio conversions with up to eight input channels (Port 0) are possible. The inputs can be selected as
single-ended or differential. The reference voltage can be internal, AVDD, or a single-ended or differential
external signal. The ADC also has a temperature-sensor input channel. The ADC can automate the
process of periodic sampling or conversion over a sequence of channels.
The battery monitor (
) (CC2533 only) enables simple voltage monitoring in devices that do
not include an ADC. It is designed such that it is accurate in the voltage areas around 2 V, with lower
resolution at higher voltages.
The random-number generator (
) uses a 16-bit LFSR to generate pseudorandom numbers,
which can be read by the CPU or used directly by the command strobe processor. It can be seeded with
random data from noise in the radio ADC.
The AES coprocessor (
) allows the user to encrypt and decrypt data using the AES algorithm
with 128-bit keys. The core is able to support the security operations required by IEEE 802.15.4 MAC
security, the ZigBee network layer, and the application layer.
A built-in Watchdog Timer (
) allows the device to reset itself in case the firmware hangs.
When enabled by software, the Watchdog Timer must be cleared periodically; otherwise, it resets the
device when it times out. It can alternatively be configured for use as a general 32-kHz timer.
USART 0 and USART 1 (
) are each configurable as either a SPI master/slave or a UART.
They provide double buffering on both RX and TX and hardware flow control, and are thus well suited to
high-throughput full-duplex applications. Each has its own high-precision baud-rate generator, thus leaving
the ordinary timers free for other uses.
The I
2
C module (
) (CC2533 and CC2541) provides a digital peripheral connection with two pins
and supports both master and slave operation.
The USB 2.0 controller (
) (CC2531 and CC2540) operates at Full-Speed, 12 Mbps transfer
rate. The controller has five bidirectional endpoints in addition to control endpoint 0. The endpoints support
Bulk, Interrupt, and Isochronous operation for implementation of a wide range of applications. The 1024
bytes of dedicated, flexible FIFO memory combined with DMA access ensures that a minimum of CPU
involvement is needed for USB communication.
24
Introduction
SWRU191C
–
April 2009
–
Revised January 2012
Copyright
©
2009
–
2012, Texas Instruments Incorporated
