Chapter 3: Hardware
V104
3-4
Two 16-bit timer units, TM0 and TM1, can operate in interval timer mode or one-shot timer mode. The
TOUT=P15 is available on pin 16 of J10.
3.2.5
Serial Channels
The V104 has three serial channels: two internal UART, SER0, SER1 and one external UART SCC2691
(U8). They can operate in full-duplex communication mode. These serial ports may be used as interrupt-
driven. For more information about the external UART SCC2691, refer to Appendix C.
The internal serial channels can operate in asynchronous mode and I/O interface mode. In asynchronous
mode, the start/stop bit transmit/receive method is employed so that bit synchronization and character
synchronization are obtained by the start bit. In I/O interface mode, data is transferred in synchronization
with the controlled serial clock. Each internal serial channel includes serial data input RxDn, serial data
output TxDn, and Clear-to-Send signal input (CTSn). Always tie CTS0 and CTS1 to GND, in order to
operate SER0 and SER1. SER0 also has a serial clock output SCKO, which outputs high level in
asynchronous mode, and functions as the transmit clock output pin in interface mode.
For SER0 and SER1, a built-in baud rate generator can be used to select standard baud rates from 110 to
1.25 M. One of these internal serial ports is used by the V104 for programming with the PC. It uses 115,000
Baud rate for programming. It is possible to use both SER0 and SER1 in applications. The user can use
SER0 to debug an application program for SER1, and then use SER1 to debug application programs for
SER0. The application programs can be combined and downloaded via either serial channel. Application
program using both SER0 and SER1 can run at the same time, but not debug at the same time.
3.2.6
Halt and Stop Mode
The V104 is an ideal core module for low power consumption applications, such as a battery operated
instrument. V25 has two standby modes, which are set by halt(); and stop(); In the HALT mode, the CPU
clock is stopped and program execution is halted, the registers are retained, and peripheral hardware
continues to function. The total power consumption is approximately 10 mA. The HALT mode is released
by interrupt input or reset input. In STOP mode, all clocks stop, but data in registers and RAM are retained.
The total power consumption is less than 4 mA. The STOP mode only can be released by NMI input or
reset input.
3.3
I/O Space Mapped Devices
External I/O device use I/O mapping. You may access I/O with inportb(port) or outportb(port,dat);. The
external I/O space is 64K, ranging from 0x0000 to 0xffff. In the I/O space of 0x0000-0x7fff, the I/O access
time is 500 ns. In the I/O space of 0x8000-0xffff, the I/O access time is 250 ns. Table 5.3 shows more
information of I/O mapped devices:
I/O space
time(ns)
Decodes
Usage
----------------------------------------------------------------------------------------------------------------------
0x0010-0x3fff
>500 ns
USER
0x4000-0x40ff
>500 ns
lcd3
0x4100-0x41ff
>500 ns
lcd4
0x8000-0xbfff
>250 ns
RTC
0xc000-0xc0ff
>250 ns
E=SCC
0xc100-0xc1ff
>250 ns
PPI
Table 3.1 Information for interface with I/O space mapped devices
3.3.2
Programmable Peripheral Interface (82C55A)
U11 PPI (82C55) is a low-power CMOS programmable parallel interface unit for use in microcomputer
systems. It provides 24 I/O pins that may be individually programmed in two groups of 12 and used in
three major modes of operation.
