Acquiring and Viewing Disassembled Data
2–10
TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Table 2–8 shows cycle type labels for ARTRY, DRTRY, and Data Error cycles,
and gives a definition of the cycle they represent.
Table 2–8: Cycle type labels for ARTRY, DRTRY, and Data Error cycles
Cycle type label
Definition
( DATA_RETRY )
Sequence with the DRTRY* signal asserted
( 60X_DATA_ERR )
Data error in the selected PPC60X data; the TEA* signal is
asserted
( ALT_DATA_ERR )
Data error in Alternate masters data
( ARTRY_CYCLE )
Sequence with the ARTRY* signal asserted
( UNKNOWN )*
Cycle with out valid information
*
If acquired with the DRTRY Included clocking option, the cycle following a valid data
cycle is always acquired in anticipation of a Data retry. If that cycle does not have any
valid information, the cycle is not displayed.
Table 2–9 shows cycle type labels for general cycle types (not sequence types),
and gives a definition of the cycle they represent.
Table 2–9: General cycle type labels definitions
Cycle type label
Definition
( FLUSH )
An instruction that was fetched but not executed
( FLUSH: PREDICTION FAIL )
An instruction that was fetched based on the prediction bit, but
the prediction bit was incorrect
( CACHE FILL )
Burst read transfer that occurrs after the wrap around of the end
of the cache line
( CLEAN BLOCK )
Clean Block transaction
( WRT WITH FLUSH )
Write-with-Flush operation issued by the microprocessor
( FLUSH BLOCK )
Flush Block transaction
( WRT WITH KILL )
Write-with-Kill transaction
( SYNC )
Address Only transaction due to the execution of Sync instruction
( DATA READ )
Single Beat Read or Burst Read operation
( KILL BLOCK )
Kill Block transaction
( RWITM )
Read-with-Intent-to-Modify transaction
( ORD I/O OPRN )
Ordered I/O operation
( WWF-ATOMIC )
Write-with-Flush-Atomic operation issued by the microprocessor
( EXT CTR WD WRT )
External Control Word Write transaction
( TLB INVAL )
TLB invalidate transaction issued by the microprocessor
