Tektronix 318, Техническое руководство

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TM 11-6625-3145-14
Theory of Operation-318/338 Service
Data Buffers, Delay Lines, and First Lactches. Data acquired by the P6451 probe is sent differentially to a data buffer.
The output of the data buffer is routed to a delay line which is used to adjust the setup/hold timings between data and
clock. This delayed data is latched by the first latch. Glitch recognition is also performed by the IC containing this latch.
External Clock Circuit. An external clock from the P6107 probe is buffered by the FET buffer and converted to ECL level
by the ultra-fast comparator. Clock delay is adjusted by a delay line with taps connected to the output of the comparator.
Clock Selector. The internal clock, or the external clock’s rising or falling edge, can be selected with this selector.
Word Recognizer. Three kinds of word recognition (Word A, B, and C) are performed by the word recognizer (WR). The
outputs of the first latches are supplied to these WRs.
Threshold Circuit. The ROM/Threshold board provides threshold levels for each of the parallel data probes and for the
external clock probe.
ACQUISITION CONTROL BOARD (A03)
This board controls all parallel data acquired through J3 on the Mother board.
Qualifier Selector. Qualifier signals from the parallel data inputs are selected by the qualifier selector as either a trigger
qualifier or a clock qualifier. Polarity is also selected by this circuit.
Strobe Generator. The strobe generator provides four timing clocks to control triggering and data writing. All timing
clocks are adjustable by tapped delay lines and variable capacitors. This generator is enabled by the clock qualifier signal.
Trigger Sequencer. The trigger sequencer performs complex triggering according to the data written in the Sequencer
RAM (SQRAM). Three outputs from the word recognizers, and the outputs from the glitch trigger are connected to the
SQRAM inputs. The trigger sequencer sets the various flags on each word recognition and, once the trigger combination
is satisfied, starts the delay counter.
Event/Delay Counter. LSI-A, specially developed by Sony/Tektronix, contains a 16-bit synchronous counter used as the
event/delay counter. This counter has two functions: trigger event counting and delay counting.
ACQUISITION MEMORY BOARD (A04)
100 MHz Oscillator. A 100 MHz crystal-controlled oscillator is used for asynchronous parallel acquisition. This clock is
divided by a 1-2-5 sequence with LSI-B (A04 U140), to produce a 20 ns to 500 ms range.
Sampled Data RAM and Glitch RAM. In the 318, a 32 X 256-bit high-speed RAM is used for storing both sampled data
and glitch data. In the 338, a 32 X 256-bit high-speed RAM is used for sampled data, and a separate 8 X 256-bit RAM is
used for glitch data.
Acquisition Address Counter and Carry Flag F-F. Two 4-bit synchronous counters are used as acquisition address
counters to provide addresses for the sampled data RAM and glitch RAM. The carry flag F-F holds the carry condition
once the address counter is full.
Output Multiplexer. Data written in the sampled data RAM, the glitch RAM, and the acquisition status register can be
read by the MPU. This multiplexer selects the data to be sent to the MPU.
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