Tektronix 318, Техническое руководство

Страница: 277 / 555

TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
Latches U106 and U108 (hex D master-slave flip-flop, 10176) on the A03 board are set to hold data 1100
binary
for the
SQRAM. They also enable U140 (hex AND-gate, 10197) and U154 (quad 2-input AND-gate, 10104) on the A03 board.
Those gates control the data supplied to the address line of the SQRAM.
The MPU writes the data already set in the latches into the SQRAM at address FF
hex
using the WRITE SQRAM signal
from U112 <6> (10162) on the A03 board. This data generates the LOAD N command for the Event/Delay Counter. After
this setup, latches U106 and U108 (10176) are written to set the clock qualifier to off, which enables the MPU to send a
single clock. The MPU generates STEP CLK by writing at I/O address 55he., from U1 10 (10162) on the A03 board, using
FF
hex
as data. That is, the SQRAM delivers the data at address FF
hex
as pointed to by the MPU. Event/Delay counter data
(LOAD N), and the Strobe Generator circuit on the A03 board generate the TRIG CLK signal to the Event/Delay counter.
By this procedure, the value of the N-register in the Event/Delay counter is loaded into the counter itself.
To keep the Event/Delay Counter enabled during the test, the SQRAM must supply CE to the Event/Delay Counter. So,
the same setups mentioned above are repeated in order to load 0000
binary
into the SQRAM.
After that, the MPU unmasks the interrput of the Event/Delay Counter Carry by writing at I/O address 40
hex
.
Then the MPU generates STEP CLK by writing FF
hex
for the SQRAM address until it receives an interrupt signal. Once the
interrupt occurs, the MPU reads the status from I/O address 5D
hex
. The signal path for reading the status is same as in
the Clock Test.
The MPU checks to see whether the Event/Delay Counter Carry Flag is set, and also checks the number of STEP CLKs
generated. If the flag is set and the clock count is correct. the MPU proceeds to the next step, otherwise it issues an error
message and stops the test.
The DELAY count can be tested in the same way as the Event count, N. In this case, 1010
binary
is set in latches U106 and
U108 (10176) on the A03 board.
7-24