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TM 11-6625-3145-14
Theory of Operation-318/338 Service
N Flag Circuit. The N flag circuit consists of A03U150B, A03U152B, and A03U152A.
The output of the carry flag of the event/delay counter N-1 (contained in LSI-A) goes low when Word A has been counted
N-1 times. N-1 connects to the inputs of the N flag flip-flop.
The N-1 flag is set to high at the next word A, and held high until trigger word B arrives.
When reset word C arrives before trigger word B, the LOADN signal is issued from the SQRAM and the N flag is reset.
TRIG’D Flag Circuit. The TRIG’D flag circuit consists of A03U150A and A03U156C <7>. When the trigger word arrives
from the parallel data probe, the LOAD DL signal from the SQRAM goes high, and the TRIG’D flag is set at the rising edge
of the trigger clock. At the same time, the con- tents of the DL register are loaded into the event/delay counter and the
delay counting is started. The trigger circuit is looped through A03U156, so the flag can not be reset until the acquisition
cycle is complete.
SUCCEED Flag Circuit. The SUCCEED flag circuit consists of A03U148, A03U156B, and A03U154.
This flag is used only when the trigger mode is a three-word successive trigger sequence, such as "WA followed by B
followed by C," or "WA then B then C,’ or "WA followed by B then C.’
In this mode, when word B arrives from the parallel data probes, the SUCCEED signal from the SQRAM goes high, and
the SUCCEED flag is set at the rising edge of the trigger clock. The TRIG’D flag follows the SUCCEED flag when word C
is acquired.
If the acquired data could not form a successful trigger sequence, the LOADN signal is issued from A03U144 <7> to reset
the N flag and the SUCCEED flag.
STOP Flag Circuit. The STOP flag circuit consists of A03U154D, A03U148A, A03U122C, A03U156A, and A03U156D
<7>.
The STOP flag is set after the delay counter in LSI is counted out; it disables three circuits as follows:
1.
Prohibits write operations to the ACQ memory by forcing the WE signal line high.
2.
Disables the input clock by reseting the START flag flip-flop A03U124B <6>.
3.
Disables the ACQ address counter (A04U136 and A04U138 <8>) on the A04 ACQ Memory board.
When the data acquisition is restarted, the stop flag will be reset by the RESET signal.
SQRAM, DATA/WORD RECOGNIZER, DATA MULTIPLEXER <7>
This circuit consists of U146<7> .It is used only for diagnostic testing of the SQRAM and the word recognizer.
LSI A A03U158 <7>
LSI-A (A03U158) is a bipolar LSI circuit designed by Sony/Tektronix.
LSI-A includes an address decoder, 16-bit N register, 16-bit DL register, 16-bit synchronous preloadable counter with fast-
carry propagation logic, the mask register, and the acquisition status logic.
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Страница 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
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Страница 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Страница 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Страница 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Страница 548: ...TN 11 6625 3145 14 Figure 9 11 318S1 338S1 A07 Serial RS232 Non Volatile Memory Board Component Locations ...
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Страница 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
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Страница 555: ...PIN 058584 ...