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TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
Table 7-19
338 WORD RECOGNIZER TEST PORT ADDRESSES (Hex)
Address
Content of Looping Test
03
increment WR-address counter for WRO test.
5B
write WRO data 55 into data latch.
5B
write WRO data AA into data latch.
03
increment WR-address counter for WR1 test.
5B
write WR1 data 55 into data latch.
5B
write WR1 data AA into data latch.
The ERROR looping feature is available only if errors are detected. If no errors are detected, the test will perform as if the
LOOP field were set to OFF. If some errors are detected, the ERROR looping function is available for the read cycle of the
test, and the result of this verification will appear on the screen. Refer to
in this manual for a description of
error codes.
Description: Refer to Figure 7-39. On the A01 INPUT-A board, data from channels 8 through 31 are latched by U100
through U1 10 (4-bit binary conter, F10016), and are then supplied to the word recognizers (WR) U118, U120 and U122
(256 word X 4-bit RAM, HM10422) eight channels at a time for trigger detection. U100 through U110 are used as both
latches to acquire data, and as WR counters to set up the WRs.
On the A02 INPUT-B board, data from channels 0 through 7 (Pod-A) is latched by M218s U200 through U214 (logic
analyzer INPUT, M218). The same data is also supplied to WR U128 (HM10422), and these output lines are wired
together, respectively, with U220 and U222 (F10016) and are used as a WR counter to set up the WR.
During acquisition, U100 through U1 10 on the A01 board are clocked to latch data coming from the parallel data probes.
PE (Parallel Load Enable) is forced high by U228A (quad 2-input NOR gate, 10102) on the A02 board. This control signal
is delivered from U234 (hex D master-slave flip-flop, 10176) on the A02 board when the MPU writes XX1XXX
binary
serially
to I/O address 03
hex
.
The outputs of U220 and U222 on the A02 board are held low by MR (Master Reset) from U114 (quad TTL-to-ECL
translator, 10124), which is generated by U1 12 (3-line to 8-line decoder/demultiplexer, 74LS138) on the A01 board when
the MPU writes any data to I/O address 02
hex
.
During WR setup, all eight F10016s are set to count enable for the counting operation by U234 (10176) on the A02 board.
The output, XX0XXX
binary
, is written serially by the MPU to I/O address 03
hex
. The enable bit is also converted to TTL
swing and then shifted to -5V by U232 (dual comparator, uPC393C) on the A02 board to set the M218’s output to off.
With the above operation, all F10016s can address the WRs. They are incrementally clocked by SYSCLK from U228B
(high-speed dual 3-input 3-output NOR gate). The word written into the WR U118 on the A01 board and the WR U218 on
the A02 board is provided with EDBO, EDB1, and EDB2. The word written to WR U120 and U122 on the A01 board is
provided with EDB3, EDB4, and EDB5. These signals are all delivered from the A04 ACQ Memory board after being
translated from TTL-level to ECL-level.
7-107
Содержание 318
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Страница 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Страница 269: ...TM 11 6625 3145 14 Maintenance Troubleshooting 318 338 Service Figure 7 7 318 Word recognizer test ...
Страница 278: ...TM 11 6625 3145 14 Maintenance Troubleshooting 31 8 338 Service Figure 7 10 318 N and DELAY counter test 7 25 ...
Страница 313: ...TM 11 6625 3145 14 Figure 7 19 Troubleshooting Tree 8 Data Acquisition ACQ A01 A02 Sheet 4 of 6 7 60 ...
Страница 344: ...338 TROUBLESHOOTING TREES ...
Страница 362: ...TM 11 6625 3145 14 Maintenance Troubleshooting 318 338 Service 4434 567 Figure 7 39 338 Word recognizer test 7 109 ...
Страница 371: ...TM 11 6625 3145 14 Maintenance Troubleshooting 318 338 Service 4434490 Figure 7 42 338 N and DELAY counter test 7 118 ...
Страница 421: ...TM 11 6625 3145 14 Maintenance Troubleshooting 318 338 Service Figure 7 55 Troubleshooting Tree 12 T H A01 A02 7 169 ...
Страница 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Страница 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Страница 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Страница 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Страница 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Страница 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
Страница 526: ...TM 11 6625 3145 14 ...
Страница 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
Страница 532: ...TM 11 6625 3145 14 ...
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Страница 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Страница 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Страница 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Страница 548: ...TN 11 6625 3145 14 Figure 9 11 318S1 338S1 A07 Serial RS232 Non Volatile Memory Board Component Locations ...
Страница 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Страница 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
Страница 554: ......
Страница 555: ...PIN 058584 ...