Tektronix 2213, Инструкция по эксплуатации

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Theory of Operation—2213 Service
the Swp Z-Axis current already present from CR622 to
intensify the display. The non-intensified portion o f the
trace indicates the amount o f total delay time.
D LY 'D . In this position o f HO RIZO NTAL MODE
switch S650, the start o f the sweep is delayed by the
amount o f time established by the Delay circuit. When a
trigger signal clocks U603B to produce a HI Swp Gate
signal on U603B pin 9, the delay time is started. The HI is
applied to the base of Q624 via R613 to bias that transistor
o ff. Transistor Q624 is used as a switch across the delay
tim ing capacitors. When biased on, the transistor keeps the
tim ing capacitors discharged. When the transistor is biased
o ff, the delay tim ing capacitors are allowed to charge. Both
the amount o f capacitance and the charging voltage are con­
trolled by D ELAY TIME switch S660. The DELAY TIME
switch also controls the voltage range applied to M U LT I­
PLIER potentiom ter R658.
For the longest delay-time range (0.2 ms), S660 switches
C622 in parallel w ith C624. When switched to the 10
-/lis
delay position, C622 is out o f the delay tim ing circuit.
Finally, in the 0.5-/us position, additional charging current
is supplied to C664 via R692 to increase the charging rate,
and +8.6 V is applied to the M ULTIPLIER potentiometer
via R600. The increased voltage changes the control range
available at the wiper o f R658.
A t the start o f the delay time, U603B pin 8 goes LO.
This removes the positive bias from Q632, and the emitter
voltage of Q632 becomes near ground potential. As the
delay tim ing capacitor charges, the base o f Q632 remains at
a constant voltage, therefore the base o f Q652 goes negative.
When the base o f comparator transistor Q652 reaches a
more negative level than the base o f comparator transistor
Q644 (set by the M ULTIPLIER control), Q652 starts to
switch o ff and Q644 starts to switch on. The collector
voltage drop o f Q644 is coupled back to the em itter o f
Q632 via R641 to complete the switching action. The
collector voltage o f Q652 rises to a HI logic level which
is applied to Sweep Logic Gate U620 on pins 3 and 13. The
HI is ANDed w ith the HI Swp Gate signal already present
to produce a LO o utput at U620 pin 6 and pin 8. The LO
at pin 6 initiates a Sweep, and the LO at pin 8 unblanks
the crt.
In the D LY 'D Mode, pin 12 o f U607D is LO, so pin 11
w ill be HI to bias CR619 on and CR621 o ff (Figure 3-6).
This action prevents intensifying current from reaching the
Z-Drive line during the D LY 'D Sweep display.
During Sweep retrace time, CR621 is biased o ff by the
HI applied to CR668 from U603B pin 8 to keep the crt
blanked off.
AUTO INTENSITY
AND Z-AXIS AMPLIFIER
Auto Intensity
The purpose o f the A u to Intensity circuit, shown in
Diagram 6, is to keep the intensity o f the trace on the crt
at a constant level w ith changing sweep speeds and trigger
signal repetition rates. In conventional oscilloscopes, as
the duty cycle o f the displayed trace changes, the intensity
w ill vary. The Auto Intensity circuit compensates for this
effect by increasing the Z-Axis Drive voltage fo r low Sweep
duty factors. The elements o f the A uto Intensity circuit
consist o f four blocks: the duty-cycle averager, the boost-
factor converter, the intensity-control m ultiplier, and the
crt triode compensation circuit. The duty-cycle averager
consists o f an electronic switching circuit composed o f
U825A, U825B, and U825C. The Swp Duty signal that is
applied to U825B pin 11 causes the output voltage at pin
14 to be switched between ground and +5 V. The output
voltage o f U825B is averaged by R821 and C821 and
applied to U835A pin 3 via U825C.
As the sweep duty factor decreases, the crt beam current
must be increased to maintain a constant intensity. To
accomplish the task, the boost-factor converter increases
the drive in inverse proportion to the duty factor o f the
trace being displayed.
A m plifier U835A is a high-impedance voltage follower.
For 100% duty factor, the output voltage w ill be approxi­
mately zero. Decreasing the duty factor to 10% results in
approximately 4.5 V output, and when no sweep occurs
(0% duty factor) the output w ill be 5 V. The output o f
U835A is applied to a network consisting o f CR828,
CR830, and resistors R827, R828, R829, R830, and R831.
This network produces an output current which is a non­
linear function o f the duty-factor voltage. For 10% duty
factor, the output current is 10 times greater than the
current at 100% duty factor. Maximum available boost
lim its at a factor o f about 25:1.
The nonlinear current is connected to the emitters of
the differential amplifier composed o f Q811 and Q812.
The emitters o f the tw o amplifier transistors are held at a
constant voltage by the action o f Q813. AUTO INTEN­
SITY control R807 is connected to the base o f Q 811 via
R811. It controls the portion o f the boost current that goes
to the summing junction o f U835B. Boost current is pro­
portional to the true beam current required at the faceplate
o f the crt.
The c rt triode compensation circuit is an inverting
operational amplifier w ith nonlinear feedback. It is
composed o f U835B, R834, R835, C834, and CR834.
O utput voltage o f the circuit changes in response to the
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