2.9.7 THE QUESTIONABLE CONDITION REGISTERS
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The bit assignments for the Questionable Condition Registers are:
BIT
NUMBER
DECIMAL
VALUE
BIT
SYMBOL
DESCRIPTION
0
1
0
Not used in Point-to-Point Mode
Instrument Summary in Multi Drop Mode
1
2
AC
AC Fail
2
4
OTP
Over Temperature
3
8
FLD
Fold Back Protect
4
16
OVP
Over Voltage Protection
5
32
SO
Shut Off
6
64
OFF
Output Off
7
128
ENA
Output Enable
8
256
INPO
,QWHUQDO,QSXW2YHUÀRZ
9
512
INTO
,QWHUQDO2YHUÀRZ
10
1024
ITMO
Internal Time Out *
11
2048
ICOM
Internal Comm Error *
12 to 15
N/A
0
Not used
Table 4.
The Questionable Registers
*: Event registers, reading will clear the event bit.
2.9.7.1 THE QUESTIONABLE CONDITION ‘CONDITION’ REGISTER
See the READ QUESTIONABLE CONDITION ‘CONDITION’ REGISTER COMMAND (STATUS:
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error conditions under which the power supply is operating.
2.9.7.2 THE QUESTIONABLE CONDITION ‘ENABLE’ REGISTER
See the READ QUESTIONABLE CONDITION ‘ENABLE’ REGISTER COMMAND (STATUS:
QUESTIONABLE:ENABLE?),
the SET QUESTIONABLE CONDITION ‘ENABLE’ REGISTER COMMAND (STATUS:
QUESTIONABLE:ENABLE) and Table 4.
The QUESTIONABLE CONDITION ‘ENABLE’ REGISTER is a mirror of the QUESTIONABLE
CONDITION ‘CONDITION’ REGISTER.
If any bit is set in the Questionable Condition ‘Condition’ Register and enabled in this reg-
ister, the condition will propagate to the Questionable Condition ‘Event’ Register as an
event.
2.9.7.3 THE QUESTIONABLE CONDITION ‘EVENT’ REGISTER
See the QUESTIONABLE CONDITION ‘EVENT’ REGISTER COMMAND (STATUS:
QUESTIONABLE:EVENT?) and Table 4.The QUESTIONABLE CONDITION ‘EVENT’ REGISTER
is a mirror of the QUESTIONABLE CONDITION ‘CONDITION’ REGISTER. If any event is set in this
Register, it will propagate to the Status Byte Register as a Questionable Summary event.
Содержание Genesys Series
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