TDK-Lambda Genesys Series, Руководство пользователя

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ƒ EVENT REGISTERS: These contain bits that are set when an event or error oc-
curs. The bits are cleared when the contents of the register are queried.
2.9.3 CLEAR ALL STATUS REGISTERS
*
CLS
This command clears all event registers and stored error messages. It will not
affect the Conditional, Instrument Summary or the Enable registers.
2.9.4 SERVICE REQUESTS AND STATUS BYTE REGISTER
The Status Byte Register contains the bits that are set when an event occurs in:
Questionable Condition Event Register,
Operational Condition Event Register,
Standard Event Status Register,
or when
a message is available in the Output Queue
or when
an Error Message is available in the Error Queue.
If any of these bits are set, and the corresponding bit is set in the Service Request Enable
Register the Service Request Bite (SRQ) bit will become set.
The SRQ bit will assert a signal onto the Service Request (SRQ) line in the IEEE cable. The
controller program can detect the SRQ, read what the problem is from the power supply,
and clear the SRQ.
The bit assignments for the Status Byte Register are:
BIT
NUMBER
DECIMAL
VALUE
BIT
SYMBOL
DESCRIPTION
0 1 BSY 1 = Busy, 0 = Ready
1 2 0 Not Used
2 4 SYS System Error, Message Available in Error Que.
3 8 QUE Questionable Summary
4 16 MAV
Message Available in Output Que.
Set after query message is received
5 32 ESB Standard Event Summary
6 64 RQS
Request For Service. Is set if SYS, QUE,
MAV, ESB and/or OPR is enabled and set.
7 128 OPR Operational Summary
Table 1. The Status Byte Register
2.9.4.1 THE SERVICE REQUEST ENABLE REGISTER
See the SET SERVICE REQUEST ENABLE COMMAND (*SRE). With two exceptions, the Service
Request Enable Register is a mirror of the Status Byte Register. Bit 0 (Busy) and Bit 6 (SRQ) will be
ignored. Also note that Bits 1 is not used in this interface and will have no effect.
To enable a Service Request, the user should refer to Table 1 and determine which events need to