Specifications are subject to change without notice
MT5362ANG/B
Approval Datasheet
Page 15 of 35
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
5
PIN DESCRIPTION of MT5362ANG/B
Pin Number Symbol
Type Driving
Description
Note
Miscellaneous
AB11 ORESET_
I
N/A
Chip
reset
1
B12
TP_VPLL
O
N/A
VPLL test port
JTAG
AC1
JRTCK
O
2~8 mA
CPU ICE Reference clock
AD2
JTCK
I
N/A
CPU ICE test clock
AC2
JTDI
I
N/A
ICE test data input
AC3
JTDO
O
2~8 mA
CPU ICE test data output
AB3
JTMS
I
N/A
ICE test mode select
AD3
JTRST_
O
2~8 mA
CPU ICE test reset
Serial / NAND flash
D20
PDD0
I/O
2~8 mA
NAND Flash Data bit 0
E19
PDD1
I/O
2~8 mA
NAND Flash Data bit 1
A19
PDD2
I/O
2~8 mA
NAND Flash Data bit 2
D19
PDD3
I/O
2~8 mA
NAND Flash Data bit 3
C19
PDD4
I/O
2~8 mA
NAND Flash Data bit 4
B19
PDD5
I/O
2~8 mA
NAND Flash Data bit 5
A18
PDD6
I/O
2~8 mA
NAND Flash Data bit 6
B18
PDD7
I/O
2~8 mA
NAND Flash Data bit 7
A16
POCE0_
O
2~8 mA
Chip enable of Serial Flash bank 0
C20 POCE1_
O
2~8
mA
Chip enable of Serial Flash bank 1 / NAND
Flash chip enable
D18
PARB_
I/O
2~8 mA
NAND Flash R/B
C17 PAALE
O
2~8
mA NAND Flash ALE
B17 PACLE
O
2~8
mA NAND Flash CLE
D17
POWE_
O
2~8 mA
NAND Flash write enable
C18
POOE_
O
2~8 mA
Serial Flash Clock / NAND Flash RE_
UART
AC8
U0RX
I
N/A
UART 0 data receive
1
AB8
U0TX
O
2~8 mA
UART 0 data transmit
1
IIC
AE4
OSCL0
O
2~8 mA
Clock for synchronal serial interface 0 (SCL)
AD4
OSCL1
O
2~8 mA
Clock for synchronal serial interface 1 (SCL)
E21
OSCL2
O
2~8 mA
Clock for synchronal serial interface 2 (SCL)
AF3
OSDA0
I/O
2~8 mA
Data for synchronal serial interface 0 (SDA)
AD5
OSDA1
I/O
2~8 mA
Data for synchronal serial interface 1 (SDA)
D21
OSDA2
I/O
2~8 mA
Data for synchronal serial interface 2 (SDA)
PWM
AF2
OPWM0
O
2~8 mA
PWM output signal 0
AE2
OPWM1
O
2~8 mA
PWM output signal 1
AE1
OPWM2
O
2~8 mA
PWM output signal 2
Infrared
AD11 OIRI
I
N/A
Infrared
input
1
07.FRQILGHQWLDO
OO
Reference clock
ce clock
LDO
U ICE test clock
est clock
WLD
ICE test data input
test data input
QWL
A
CPU ICE test da
CPU ICE test da
GHHHQW
H
N/A
ICE test m
A ICE
test
GHHHQ
I
H
O 2~8
mA
CP
2~8 mA
IIILGH
HH
I
H
ILG
I/O 2~8
m
I/O 2~
QQQIIIL
QI
DD1 I/O
I/O
RQQQIII
QI
PDD2
PDD2
FRQQQ
.
Q
D19 PDD3
9 PDD3
... F
R
7.
C19 PDD4
C19
77...
07.
B19 P
9
07
07...
07.
A18
A18
07
07
07
B
000
)RU7&/2QO\
Data bit 2
Flash Data bit 3
ash Data bit 3
O\
NAND Flash Data bit 4
Data bit 4
O\
2
NAND Flash Data bit 5
NAND Flash Data bit 5
222QO\
2
mA
NAND Flash Data
NAND Flash
222QO
2
2~8 mA
NAND Flas
2~8 mA
NAN
/ 222Q
&
2
O 2~8
mA
Chi
O 2~8
mA
&&&/
222
7&
2
_ O
2~8
mA
O 2~8
mA
777&&&/
7&
PARB_ I/O
2
_ I/O
7777
PAALE O
PAALE
U
)R
PACLE
PACLE
)R
)R
)RU
)R
POWE_
)R
)R
)R
)R
P
))))
1R'LVFORVXUH
UH
bank 1 /
UH
sh ALE
XUH
AND Flash CLE
ND Flash CL
VX
NAND Flash write enab
D Flash write enab
ORV
A
Serial Flash Cloc
Serial Flash Cloc
OR
F
VFO
I N/A
UA
N/A UA
'''LVF
FF
'
F
O 2~8
mA
2~8 mA
'''LV
''L
CL0 O
CL0 O
1R
''''
CL1
L1
1R
2
1R
1
