Specifications are subject to change without notice
MT5362ANG/B
Approval Datasheet
Page 25 of 35
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
R16 DVSS
I
N/A
Core
ground
R18 DVSS
I
N/A
Core
ground
T10 DVSS
I
N/A
Core
ground
T11 DVSS
I
N/A
Core
ground
T12 DVSS
I
N/A
Core
ground
T13 DVSS
I
N/A
Core
ground
T14 DVSS
I
N/A
Core
ground
T15 DVSS
I
N/A
Core
ground
T16 DVSS
I
N/A
Core
ground
T17 DVSS
I
N/A
Core
ground
T5 DVSS
I
N/A
Core
ground
T6 DVSS
I
N/A
Core
ground
U12 DVSS
I
N/A
Core
ground
U14 DVSS
I
N/A
Core
ground
U16 DVSS
I
N/A
Core
ground
U18 DVSS
I
N/A
Core
ground
U2 DVSS
I
N/A
Core
ground
U4 DVSS
I
N/A
Core
ground
V2 DVSS
I
N/A
Core
ground
V3 DVSS
I
N/A
Core
ground
Y6 DVSS
I
N/A
Core
ground
Note 1 : These pins belong to the standby power domain.
Note 2 : The symbols of these pins match to their real functions under DDR2, with DRAM PINMUX
register set to 2’b00. These pins have different functions under DDR1 mode, with DRAM PINMUX
register set to 2’b01, as listed in the following table.
Pin Number
DDR1 function
Type
Driving
Description
DRAM interface
M1
RA0
O
8.1~10.1 mA
memory address bit 0
N3
RA1
O
8.1~10.1 mA
memory address bit 1
P2
RA2
O
8.1~10.1 mA
memory address bit 2
P1
RA3
O
8.1~10.1 mA
memory address bit 3
L1
RA4
O
8.1~10.1 mA
memory address bit 4
L2
RA5
O
8.1~10.1 mA
memory address bit 5
L5
RA6
O
8.1~10.1 mA
memory address bit 6
K4
RA7
O
8.1~10.1 mA
memory address bit 7
M6
RA8
O
8.1~10.1 mA
memory address bit 8
J1
RA9
O
8.1~10.1 mA
memory address bit 9
N5
RA10
O
8.1~10.1 mA
memory address bit 10
J4
RA11
O
8.1~10.1 mA
memory address bit 11
K3
RA12
O
8.1~10.1 mA
memory address bit 12
M3
RBA0
O
8.1~10.1 mA
memory bank address bit 0
M2
RBA1
O
8.1~10.1 mA
memory bank address bit 1
N6
RCAS_
O
8.1~10.1 mA
memory column address strobe
07.FRQILGHQWLDO
OO
nd
LDO
re ground
d
WLD
Core ground
e ground
WL
Core ground
Core ground
G QW
H
N/A Core
grou
A Core
gro
GHHHQ
I
H
I N/A
Cor
N/A Co
IIILGH
HH
I
H
I N/A
N/A
IIILG
QI
I N/A
I N/A
QQQIIIL
QI
DVSS I
I
RQQQIII
QI
DVSS
DVSS
FRQQQ
.
Q
V3 DVSS
3 DVSS
... F
R
.
Y6 DVSS
Y6
7...
F
07
07...
Note
Note
)RU7&/2QO\
round
und
O\
Core ground
d
O\
222QO\
by power domain.
omain.
ns match to t
ns matc
heir real functio
real fu
se pins have different
e pins have differe
functio
, as listed in the following tabl
ted in the following
RU
)RUUU
7
DD
U 7
U
AM interface
AM interfa
)RU
)RUUUUU
RA
)R
)
1R'LVFORVXUH
RA
VXUH
XUH
VXU
VXU
0.1 mA
memory address
mA
memory addre
OOORVX
O
8.1~10.1 mA
memory a
.1 mA
memory
OOORV
O
O 8.1~10.1
mA
me
O 8.1~10.1
mA
me
FOOO
L
O
O 8.1~10.1
m
O 8.1~10.1
m
LLLVF
'L
O 8.1~
O 8.1
'''LLLV
'L
RA5 O
RA5 O
'''L
1
'
RA6
RA6
111R
'
1
RA7
RA7
111R
1
RA
R
1111
