Specifications are subject to change without notice
MT5362ANG/B
Approval Datasheet
Page 16 of 35
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
D22
OIRO
O
2~8 mA
Infrared output
Power Management
AD10
OPCTRL0
I/O
2~8 mA
Power management GPIO 0
1
AC10
OPCTRL1
I/O
2~8 mA
Power management GPIO 1
1
AB10
OPCTRL2
I/O
2~8 mA
Power management GPIO 2
1
AC9
OPCTRL3
I/O
2~8 mA
Power management GPIO 3
1
AB9
OPCTRL4
O
2~8 mA
Power management GPIO 4
1
AD8
OPCTRL5
O
2~8 mA
Power management GPIO 5
1
AC11
OPWRSB
O
2~8 mA
Power switch on/off
1
AC13 HDMI_CEC
I
N/A
CEC
control
1
AD16
PWR5V_0
I/O
2~8 mA
HDMI Rx 0 power enable
1
AB16
HDMI_SDA0
I/O
2~8 mA
HDMI Rx 0 DDC-CI bus
1
AC16
HDMI_SCL0
I
N/A
HDMI Rx 0 DDC-CI bus
1
AD14
PWR5V_1
I/O
2~8 mA
HDMI Rx 1 power enable
1
AC14
HDMI_SDA1
I/O
2~8 mA
HDMI Rx 1 DDC-CI bus
1
AC15
HDMI_SCL1
I
N/A
HDMI Rx 1 DDC-CI bus
1
AD12
PWR5V_2
I/O
2~8 mA
HDMI Rx 2 power enable
1
AB12
HDMI_SDA2
I/O
2~8 mA
HDMI Rx 2 DDC-CI bus
1
AC12
HDMI_SCL2
I
N/A
HDMI Rx 2 DDC-CI bus
1
DRAM interface
K3
RA0
O
8.1~10.1 mA
memory address bit 0
2
N6
RA1
O
8.1~10.1 mA
memory address bit 1
2
L1
RA2
O
8.1~10.1 mA
memory address bit 2
2
N5
RA3
O
8.1~10.1 mA
memory address bit 3
2
M6
RA4
O
8.1~10.1 mA
memory address bit 4
2
M4
RA5
O
8.1~10.1 mA
memory address bit 5
2
L2
RA6
O
8.1~10.1 mA
memory address bit 6
2
M2
RA7
O
8.1~10.1 mA
memory address bit 7
2
L5
RA8
O
8.1~10.1 mA
memory address bit 8
2
M3
RA9
O
8.1~10.1 mA
memory address bit 9
2
M5
RA10
O
8.1~10.1 mA
memory address bit 10
2
K4
RA11
O
8.1~10.1 mA
memory address bit 11
2
M1
RA12
O
8.1~10.1 mA
memory address bit 12
2
N3
RBA0
O
8.1~10.1 mA
memory bank address bit 0
2
P2
RBA1
O
8.1~10.1 mA
memory bank address bit 1
2
J1
RCAS_
O
8.1~10.1 mA
memory column address strobe
2
N4
RCKE
O
8.1~10.1 mA
memory clock enable
2
H2
RCLK0
O
8.1~10.1 mA
memory clock 0 positive
H1
RCLK0_
O
8.1~10.1 mA
memory clock 0 negaitive
AB2
RCLK1
O
8.1~10.1 mA
memory clock 1 positive
AB1
RCLK1_
O
8.1~10.1 mA
memory clock 1 negative
J2
RCS_
O
8.1~10.1 mA
memory chip select
2
C4
RDQ0
I/O
8.1~10.1 mA
memory data bit 0
B2
RDQ1
I/O
8.1~10.1 mA
memory data bit 1
C3
RDQ2
I/O
8.1~10.1 mA
memory data bit 2
A2
RDQ3
I/O
8.1~10.1 mA
memory data bit 3
A4
RDQ4
I/O
8.1~10.1 mA
memory data bit 4
D5
RDQ5
I/O
8.1~10.1 mA
memory data bit 5
07.FRQILGHQWLDO
IO 5
O
ff
O
rol
LDO
MI Rx 0 power enable
power enable
WLD
HDMI Rx 0 DDC-CI bus
MI Rx 0 DDC-CI bus
WL
HDMI Rx 0 DDC-
HDMI Rx 0 DDC-
G QW
H
2~8 mA
HDMI Rx 1
8 mA
HDMI Rx
GHHHQ
I
H
I/O 2~8
mA
HD
2~8 mA
HD
IIILGH
HH
I
H
I N/A
N/A
IIILG
QI
_2 I/O
2~8
mA
I/O 2~8
mA
QQQIIIL
QI
DMI_SDA2 I/O
I/O
RQQQIII
QI
HDMI_SCL2
HDMI_SCL2
FRQQQ
.
Q
RAM interface
AM inte
. F
R
K3 RA0
K3
7...
F
07.
N6 R
R
07
07...
07.
L1
L1
07
07
07
N
N
000
)RU7&/2QO\
DC-CI bu
O\
memory address bit 0
dress bit 0
O\
2
mA
memory address bit 1
memory address bit 1
222QO\
2
~10.1 mA
memory address b
memory add
222QO
2
8.1~10.1 mA
memory ad
8.1~10.1 mA
memor
/ 222Q
&
2
O 8.1~10.1
mA mem
O 8.1~10.1
m
&&&/
222
7&
2
O 8.1~10.1
mA
O 8.1~10.1
m
777&&&/
7&
O 8.1~10.1
O 8.1
777&&&
7&
RA7 O
8
O
7777
RA8 O
RA8
U
)R
RA9
RA9
)R
)R
)RU
)R
RA10
RA10
)R
)R
)R
)R
RA
))))
1R'LVFORVXUH
H
bit 7
UH
dress bit 8
t 8
XUH
mory address bit 9
mory address bit 9
VXU
memory address bit 10
emory address bit 10
ORVX
1 mA
memory address b
memory address
OR
F
8.1~10.1 mA
memory ad
~10.1 mA
memory ad
FFFO
F
O 8.1~10.1
mA mem
8.1~10.1 mA
mem
LVFFF
'
F
O 8.1~10.1
mA
8.1~10.1 mA
'''LV
'
O 8.1~10.1
8.1~10.
'''L
'
KE O
8
KE O
8
1R
''''
LK0 O
K0
1R
K0_
0_
1R
1
