TCL 46P11FZE, Руководство по обслуживанию

Страница: 39 / 116

GND
GND GND
T
T
T
T
BS
IN
SW
COMP FB SS
GND
EN
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
BA0 BA1 CKE
CK_P CK_N
CS RAS CAS WE
VDD
VDD1
VDD2
VDD3
VDD4
VDDQ
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VSS
VSS1
VSS2
VSS3
VSS4
VSSQ
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9 VDDQ9
VDDL VREF
LDQS_P
VSSDL
LDQS_N
UDQS_P UDQS_N
LDM
UDM
ODT
BA2 A13
NC=A2,E2,R3,R7
T
T
RE3P
RE3N
REXT
GND18
VDDP4
VDDC4
AVDD_MEMPLL
GND16
GPIO_13 GPIO_14
LVD1M
LVD1P
LVD0M
LVD0P
LVC4M
LVB0P
LVC3P
BADR0
BADR1
MADR1
MADR5
MADR9
MADR12
MADR11
WEZ
MADR2
MADR4
GND10
VDDP2
MADR6
LVACKP
GND2 PDI
GND19
GPIO27
GPIO26
AVDD_DDR2 DQM1 AVDD_DDR1 MDATA6
MADR10
AVDD_DDR6
MDATA8 AVDD_DDR4
SDI
LVC1M
MDATA2 MDATA7 AVDD_DDR5 MDATA13 MCLK
LVA4M
LVA4P
LVA3M
AVDD_LVDS3
LVBCKP
LVBCKM
VDDP1 GPIO14
LVB3P LVB3M
VDDP6
GND21
ROCKN
ROCKP
RO3N
RO3P
RO4N
RO4P
GND22
AVDD_33_2
RE0N
RE0P
XIN
RE1N
RE1P
RE2N
RE2P
XOUT
VDDC8
AVDD_33_1
RO0N
RO0P
RO2N
RO2P
LVB0M
AVDD_LVDS2
GPIO31
SCLM2R
MADR3
LVACKM
DQM0 GND6 GND5 MDATA12 SCLS
LVCCKP
VDDC6
LVA3P
LVA1P
RO1P
GPIO11 GND7 MCLKZ
MADR0
VDDC3
GPIO_4
RESET
LVD3P
DQS1 GND3
RECKN
LVA0P
AVDD_LPLL
GND20
LVB2M LVB2P
VDDC7
CSZ
PWM1
LVD2P
PWM0 GPIO1
VDDC5 VDDP5 LVD4M
LVD4P
LVDCKM LVDCKP
GPIO25
GPIO23
GPIO24
SDAM2R
GPIO_12
GPIO_1
GND12
SDAM2L
SCLM2L
GND11
MCLKE
GPIO_11
GPIO_10
GPIO_9
GPIO_8
GPIO_6
GPIO_2
GPIO22
LVB4M LVB4P
GND14
LVC3M
MDATA1 GND4 BIST DQSB0 AVDD_DDR3 MDATA14 MDATA9 MDATA4 GPIO8 GPIO9 VDDC1 GPIO10 GPIO12 GPIO13 GND1 SDAS
LVC0M
LVC0P
GND17
AVDD_LVDS1
LVC2M
LVC1P LVC2P
CASZ
RASZ
DQS0 MDATA11 MDATA3 MDATA5 MDATA0 MDATA10
MADR7
GPIO_15
LVA2P
RO1N
VDDP3
GND13
LVD3M
LVCCKM GPIO_16
LVA1M
LVA0M
AVDD_MPLL
DQSB1 VDDC2
SDO
LVC4P
RECKP
GND8 MDATA15
LVA2M
AVDD_LVDS
RE4N
GND9
ODT
MADR8
GPIO_3
GPIO_5
GPIO_7
GND15
SCK
LVD2M
LVB1P
LVB1M
RE4P
EP
217
DIO
CLK
HOLD
VCC
GND WP DO CS
T
T
T
T
T
T
CHIP_CONF= {1,1,1}: boot from SPI CHIP_CONF= {1,1,0}: boot from EEPROM CHIP_CONF= {1,0,1}: boot from internal SRAM CHIP_CONF: {SET2, SET1, SET0}
Chip Config
GPIO1 IS ALWAYS LOW
MEMC SPI-FLASH
MEMC DDR2
MEMC Chip PAGE
1.28V@1A
SDA SCL
3V3
GND
4U7 CM148
I2C_SDA
0.1U
CM176
CM78
100U
16V
CM458
10U
4K7
RM84
1K
RM85
22K
RM87
RM68
4K7
4K7
RM67
MEMC_3V3
MEMC_3.3V
SPI2_WP
SPI2_DI
SPI2_DI
SPI2_CLK
SPI2_FLASH_WP
SPI2_CS
SPI2_DO
RM99
200R
5 6 7 8
4 3 2 1
UM19
W25X40A
214
213
162 161
107
108
54
128 129 130 131 132 133 134 135
166
138
67
66
68
71
72
73
64
65
59
60
61
36
62
174
6
12
167
104
103
29 30 23 22
69
70
42 40
111 143
49 47 46 45 51
169
170
171
168
154 153
15 14
152 151
184
185
197
198
199
200
201
202
203
204
205
206
186
207
208
209
210
187
189
190
191
192
195
196
165
160
98
97
75
173
31 32 26 25
3
140 159
172
178
194
9
37 52
58
78
86
106
122
38 16
211
180
181
182
155 156
183
113 114 127 115 116 117 118 119 120 124 125
102
100
101
96
95
83
82
80
79
77
76
94
93
91
90
88
84
99
149 150
105
137
21 20 13 34 35 28 27 18
4 5 7 8
10 11
1 2
145 146 147 148 141 144 142
57
56
33 24 19 50 48 44
74
157
176
193
81
92
121 139 158
177
179
188
39 17
112 136
212
43 41
175
123
216
215
53
55
63
85
87
89
109 110 126
164
163
UM21
MST6M20S
M81_SCL
M81_SDA
MEMC_3.3V
M81_SDA M81_SCL
OSDA0
OSCL0
0R R198
ZM7
ZM61
CM200
1U
CM160 0.1U
AVDD_DDR2
3K6
RM98
8 6
3 1 27 45
47R
RM131
RM106
47R 47R
RM107 RM102
47R
RM110
NC/150R
RM105
47R
8
6 3
1
2 7
4 5
NC/1K RM361
5 4
7 2
1
3 6
8
RM360 NC/1K
8
6 3
1
2 7
4 5
NC/1K RM359
5 4
7 2
1
3 6
8
RM358 NC/1K
R8
L1
K9 B3 F3 A8 B7 E8
J7
F7 J2
J1
G9 H8
H2
F8
F2
E7
D8
D2
B8
B2
A7
P9
N1
J3
E3
A3
G7
G3
G1
E9
C9
C7
C3
C1
A9
R1
M9
J9
E1
A1
K3 L7 K7
L8
K8
J8
K2
L3 L2
B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8
R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8
HYB18TC1G160C2F
UM18
CMCLKN
CMCLKP
NC/4K7
RM186 RM185
NC/4K7
5
4
7
2 1 36
8
RM362
NC/1K
RM242
NC/4K7
NC/4.7K
RM77
NC/4K7
RM66
RM64
NC/4K7
NC/4K7
RM62
NC/4K7
RM24
CM3 1U
CM2
4U7
CM1
220U
6V3
DM201
NC/SK24
RM312
100R
RM311
100R
RM310
100R
R11
100R
RM308
100R
RM307
100R
RM306
100R
RM305
100R
RM304
100R
RM303
100R
RM302
100R
RM301
100R
MS_GPIO10
VDDC2
LVDS2_0N
MEMC_3.3V
AVDD_MPLL2
CM116
470U 6V3
RM100 820R
CM321 10U
VDDC2
LVDS1_0N
L186 120R
1 2 3
6 5 8
4
7
UM20
MP1482
CM124
22P
22P
CM125
XM2
12M
URSA_D4N URSA_D4P URSA_D2P
URSA_ACKP
URSA_A0N
URSA_B0P
URSA_BCKP
URSA_B4P
12V
CM175
0.1U
CM144
0.1U
2
3
1
0BAV99
DM8
RM25
4K7
RM65
4K7
4K7
RM63
RM29
4K7
AVDD_MEMPLL2
AVDD2
C_BA2
SET0
0.1U
CM122
CM155
0.1U
0.1U CM157
0.1U CM153
CM158 0.1U
0.1U
CM123
100R
RM72
AVDD_LVDS2 AVDD_LPLL2
CM119
1U
VDDC2
URSA_A1P
MEMC_DDR2_1V8
5
4
7
2 1 36
8
RM128
47R
0.1U CM161
CM162 0.1U
0.1U CM165
CM166
0.1U
220R
LM53
54 72
1 3
6 8
RM126
47R
URSA_B3P
URSA_B1N
AVDD_LPLL2
URSA_A3P URSA_D0P URSA_C0N
URSA_C2P
URSA_C4P GPIO1
URSA_B2P
AVDD_LVDS2
URSA_A2P
URSA_A3N
URSA_C3N
URSA_C2N
DDR2_VREFC
C_CKE
C_MADR3
C_MADR7
C_MADR12
C_MADR9
C_MADR5
C_MADR10
C_MADR1
C_BA0
C_BA1
C_WEZ
C_MADR11
C_MADR8
C_MADR6
C_MADR4
C_MADR2
C_MADR0
C_CASZ
C_RASZ
C_ODT
C_MCLKN
C_DQS0M C_DQS0P
C_MDATA1 C_MDATA6 C_MDATA3 C_MDATA4
47R
RM104
MEMC_3.3V
RM88
100K
CM126
1000P
SPI2_FLASH_WP
SET2
I2C_SCL
SET0
AVDD_DDR2
VDDC2
VDDC2
AVDD2
LVDS1_3N
LVDS1_3P
AVDD_LVDS2
AVDD_LVDS2
AVDD_DDR2 AVDD_DDR2 AVDD_DDR2 AVDD_DDR2
VDDC2
VDDC2
MEMC_3.3V
MEMC_3.3V
MEMC_3.3V
VDDC2
VDDC2
URSA_B0N
LVDS2_4P
LVDS2_4N
LVDS2_0P
LVDS2_1N
LVDS2_1P
LVDS2_3P
LVDS2_3N
LVDS2_2P
LVDS2_2N
LVDS2_CLKP
LVDS2_CLKN
LVDS1_0P
LVDS1_4P
LVDS1_4N
LVDS1_1P
LVDS1_1N
LVDS1_2P
LVDS1_2N
LVDS1_CLKP
LVDS1_CLKN
URSA_A1N
URSA_B4N
URSA_B3N
URSA_BCKN
URSA_B2N
URSA_B1P
URSA_A4N URSA_A4P
URSA_ACKN URSA_A2N
URSA_C1N URSA_C1P URSA_C0P URSA_D3N URSA_D3P
URSA_DCKN URSA_DCKP
URSA_D2N URSA_D1N URSA_D1P URSA_D0N
URSA_C4N
URSA_CCKN URSA_CCKP
MEMC_3.3V
MEMC_3.3V
AVDD_DDR2
AVDD_LVDS2
AVDD2
AVDD_MPLL2
AVDD_MEMPLL2
MEMC_3.3V
MEMC_3.3V
MEMC_3.3V
MEMC_3.3V
SET1
GPIO1
SET2
MEMC_3.3V
RM76
100R
ZM42
ZM17
ZM16
4 3 2 1
PM3
I2C_SDA
I2C_SCL
SPI2_CLK
SPI2_CS
SPI2_DO
SPI2_CS
SPI2_DO SPI2_DI SPI2_CLK
RM78
1M
MEMC_3.3V
B
E C
QM7
BT3906
CM117
2U2
47R
RM113 RM112
47R 47R
RM111
47R
RM109
RM108
47R
8 6
3 1 27 45
47R
RM136
5
4
7
2 1 36
8
RM135
47R
8 6
3 1 27 45
47R
RM134
5
4
7
2 1 36
8
RM133
47R
5
4
7
2 1 36
8
RM132
47R
1K
RM91
RM90
1K
MEMC_DDR2_1V8
MEMC_DDR2_1V8
8 6
3 1 27 45
47R
RM130
8 6
3 1 27 45
47R
RM129
8 6
3 1 27 45
47R
RM127
47R
RM103
47R
RM101
CM127
1U
C_MCLKN
CMCLKN
C_MCLKP
CMCLKP
CDQS1M CDQS1P
C_DQS0M
CDQS0M CDQS1P
C_DQS1P
CDQS1M
C_DQS1M
DDR2_VREFC
C_MADR8
C_MADR11
C_RASZ
C_CASZ
C_WEZ
C_CKE
C_BA1
C_MADR9
CMADR9
C_MADR2
CMADR2
C_MDATA5
C_MDATA11
CMDATA11
C_DQM0
CMDATA15 CMDATA14 CMDATA13 CMDATA12 CMDATA11 CMDATA10 CMDATA9 CMDATA8 CMDATA7 CMDATA6 CMDATA5 CMDATA4 CMDATA3 CMDATA2 CMDATA1 CMDATA0
CMADR12 CMADR10 CMADR9 CMADR5 CMADR4 CMADR3 CMADR2 CMADR1 CMADR0
C_DQM1
C_ODT
CMDATA12
C_MDATA12
CMDATA14
C_MDATA14
CMDATA9
C_MDATA9
C_MDATA1
CMDATA1
C_MDATA6
CMDATA6 CMDATA3 CMDATA4
C_MDATA4 C_MDATA7
CMDATA7
CMDATA0
C_MDATA0
CMDATA5 CMDATA2
C_MDATA2
C_MDATA10
CMDATA10
C_MDATA13
CMDATA13
C_MDATA8
CMDATA8
CMDATA15
C_MDATA15
CMADR3
C_MADR3
C_MADR10
CMADR10
C_MADR1
CMADR1
C_MADR6
CMADR6
C_MADR4
CMADR4
CMADR0
C_MADR0
CMADR7
C_MADR7
CMADR12
C_MADR12
CMADR5
C_MADR5
C_MDATA3
C_DQS0P
CDQS0P
CDQS0P CDQS0M
CMADR7 CMADR6
C_MDATA12 C_MDATA11 C_MDATA14
C_MDATA9
C_DQM0 C_DQM1
C_MDATA8 C_MDATA15 C_MDATA13 C_MDATA10 C_MDATA0 C_MDATA7 C_MDATA5 C_MDATA2 C_MCLKP
C_DQS1P
C_DQS1M
CM151 0.1U
CM149 0.1U
0.1U CM145
0.1U
CM143
CM137
0.1U
0.1U CM135
0.1U CM132
MEMC_DDR2_1V8
0.1U CM131
URSA_C3P
VDDC2
0.1U CM159
0.1U CM156
CM154 0.1U
0.1U CM152
0.1U
CM174
220R LM52 LM51 220R LM50
220R
CM173
0.1U
0.1U CM172 0.1U CM171
CM170
0.1U
0.1U CM169
CM168 0.1U
0.1U CM167
LM49 220R
LVDS1_0N LVDS1_1P LVDS1_1N LVDS1_0P LVDS1_2N LVDS1_CLKP LVDS1_CLKN LVDS1_2P LVDS1_3N LVDS1_4P LVDS1_4N LVDS1_3P
LVDS2_3P LVDS2_4N LVDS2_4P LVDS2_3N LVDS2_2P
LVDS2_CLKN
LVDS2_CLKP LVDS2_2N LVDS2_0P LVDS2_1N LVDS2_1P LVDS2_0N
22UH
LM23
ZM76
9K1
RM97
0.01U CM178
RM95
2K2
RM94
100K
CM177
3300P
MEMC_DDR2_1V8
0.1U CM331
CM330 0.1U
220R LM59
SET1
CM129
0.1U
CM128
0.1U
0.1U CM147
0.1U CM146
4K7
RM332
MEMC_3.3V
URSA_A0P
R201 100R
C477
47P
C473
47P
R200
100R
MEMC_3.3V
DV33A
C469
0.1U
C118
100U
6V3
C_BA0