Takenaka System FC2200GE, Инструкция по эксплуатации, Страница: 46 / 58

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10. Timing Chart
● Pixel clock timing (common in various operation modes)
[Phase relationship between clock output and data]
(Note) The above timing represents the signal timing before being input to the input part of the interface unit (Camera Link
interface).
All the synchronization signals described in this chapter are internal signals as the synchronization signal
(FVAL,LVAL,CLK etc.) is not output to the outside in the case of GigE camera.
●
Horizontal timing (Common in each operation mode)
ＨＤ
Horizontal timing
ＣＣＤ output signal
ＯＢ
約４． ５
Horizontal transfer
suspension time Dummy
bit
ＯＢ
１２
E ffec tiv e p ixel s
１Hor izo ntal pe riod（ １Ｈ）
（I nte rn al h ori zo nt al
s ync hr on ou s s ig na l ）
3156
Effective image duration （２６ １６）
約 ４ ３
Ineffective image duration （５４ ０） Effective image duration
ＬＶＡＬ
Image signal
(Digital signal)
Internal
signal
Image
output
316
540
460 40 28
2616
524
2
6
1
6
1 2 3 4 5
1 2 3 4 5
2
6
1
6
2
6
1
6
※
Unless otherwise specified, the time unit of the values in the horizontal timing chart is CLK (1/32.5MHz = 30.77nS).
(Note) Excluding the case that the trigger signal (Vint) is input permitting H-reset in the asynchronous shutter mode.
1 PCLK ＝ 15.4 ns *
10ns (max)
PCLK
* 15.4ns
in the case of FC2200GE
20.8ns
in the case of FC2200GE
Digital data
12bit /
10bit /
8bit /
Clock output
Ａ／Ｄ
８～１２ｂｉｔ
(LVAL,FVAL)
PCLK
PCLK
L AN c on ne c to r
C
a
m
e
ra
L
in
k
R
J-
4
5
G
ig
E
I
/F
Co lo r c odi ng (H or izo ntal out pu t t im ing )
CCD output signal
１
Effective image
２ ４ ５ ６
２ ４ ３ ５
(Odd line）
R G R G R R G R G
２
４
５
６
２
４
５
５
G R G R R G R G G
（Even line）
G B G B B B G G B G B B G B G B G G
１
Effective image
２ ４ ５ ６
２ ４
３
５
CCD output signal
２
４
５
６
２
４
５
５
（ＦＳ５０００ ＧＥ）