SVP HDR-106, Руководство пользователя

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HDR-106 MPEG2/H264 – 4:2:2 – 10 bits – DVB-T2/T Diversity 6 – DVB-S2/S Receiver
MANUAL 7.0
Chapter 7: Block Diagram
In this chapter, the block diagram of the HDR-106 receiver is explained.
This diagram has several parts related to the HDR-106 internal performance
which are shown in blocks with different inputs and outputs.
In the first part, the different types of inputs (DVB-T, DVB-T2, ASI or IP) go
to the TS switcher block and then, one of them is selected according to the
necessities of the user. Once the input signal is selected, it passes through
the BISS-1/E block where it is decrypted according to the type of BISS
encryption employed in the transmitter.
The next block is a multiplexer which distributes the signal in four different
parts related to video, audio or data. Then, each signal goes to the
corresponding decoder (Video decoder, Audio1 decoder, Audio 2 decoder)
where the different types of video and audio are obtained. The Genlock is
used to synchronize the video signal. In this way, the different outputs are
available for the user (CVBS, SDI, HDMI, Analogue, AES-EBU, Audio 1,
Audio 2 and Remote GPS Data).
In the bottom of the diagram, there is a FPGA Controller, which is
responsible for controlling all the system. This block controls the GPS, the
antenna autotracking, the temperature and the voltage. It also has an USB
and Ethernet control connection. There is a power relay block that allows
employing DC or AC power in the equipment.