2-22
X7DVL-E User's Manual
LAN1
®
S
UPER X7DVL-E
FP Control
Fan3
IDE1
Floppy
Fan4
SATA3 SATA5
SMB
PCI 33 MHz
PCI 33 MHz
JD1
Battery
GLAN
CTRLR
PCI-Exp x8
North Bridge
COM1
ATX PWR
8-Pin
PWR
24-Pin
CPU2
South
Bridge
Fan1
SATA2 SATA4
SATA1
SATA0
Slot1
Slot2
Slot3
PCI-X 133 MHz
Slot4
JPL2
Slot5
DIMM 1A (Bank 1)
DIMM 1B (Bank 1)
DIMM 1C (Bank 1)
DIMM 2A (Bank 2)
DIMM 2B (Bank 2)
DIMM 2C (Bank 2)
JBT1
JCOM2
KB/
Mouse
USB 0/1
5 0 0 0 V
BIOS
LAN2
Fan5
Fan6
JPWF
JAR
PWR
I
2
C
VGA
Slot6
PCI-X 133 MHz
PCI-E x4
JPG1
JWD
Printer
JPL1
JI
2
C1
JI
2
C2
JWOR
SIMLC
JWOL
Fan2
CPU1
LE2
LE3
LE1
LE5
LE4
USB4/5
USB2/3
JPF
Buzzer
ESB2
VGA
CTRLR
SGPIO1
SGPIO2
JL1
D31
SGPIO Headers
There are two SGPIO (Serial General
Purpose Input/Output) headers located
on the motherboard. These headers are
used to communicate with the System
Monitoring Chip on the backplane. See
the table on the right for pin defi nitions.
Refer to the board layout below for the
locations of the headers.
SGPIO
Pin Defi nitions
Pin# Defi nition
Pin Defi nition
1
*NC
2
*NC
3
Ground
4
DATA Out
5
Load
6
Ground
7
Clock
8
*NC
*Note:
NC= No Connections
A
B
A. SGPIO#1
B. SGPIO#2
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