Chapter 5: Running Setup
5-7
adapter cards. The settings are:
Disabled
,
Enabled or Cached
. When set
to
Disabled,
the contents of the video ROM are not copied to RAM. When
set to
Enabled,
the contents of the video ROM area from C0000h-C7FFFh are
copied (shadowed) from ROM to RAM for faster execution. When set to
Cached,
the contents of the video ROM area from C0000h-C7FFFh are copied
from ROM to RAM and can be written to or read from cache memory.
5-1-3
Advanced Chipset Setup
USB Function
The settings for this option are
Enabled
or
Disabled
. Set this option to
Enabled
to enable the USB (Universal Serial Bus) functions.
USB KB/Mouse Legacy Support
The settings for this option are
Keyboard, Auto, KMouse
or
Dis-
abled
. Set this option to
Enabled
to enable the USB keyboard and mouse.
Port 64/60 Emulation
The settings for this option are
Enabled
or
Disabled
.
SERR# (System Error)
The settings for this option are
Enabled
or
Disabled
. Set to
Enabled
to
enable the SERR# signal on the bus. GX asserts this signal to indicate a
system error condition. SERR# is asserted under the following conditions:
- In an ECC configuration, the GX asserts SERR#, for single bit (correctable) ECC errors or
multiple bit (non-correctable) ECC errors if SERR# signaling is enabled via the ERRCMD
control register. Any ECC errors received during initialization should be ignored.
- The GX asserts SERR# for one clock when it detects a target abort during GX initiated PCI
cycle
- The GX can also assert SERR# when a PCI parity error occurs during the address or data
phase
- The GX can assert SERR# when it detects a PCI address or data parity error on AGP
- The GX can assert SERR# upon detection of access to an invalid entry in the Graphics
Aperature Translation Table
- The GX can assert SERR# upon detecting an invalid AGP master access outside of AGP
aperture and outside of main DRAM range (i.e. in the 640k - 1M range or above TOM)
- The GX can assert SERR# upon detecting an invalid AGP master access outside of AGP
aperture.
- The GX asserts SERR# for one clock when it detects a target abort during GX initiated AGP
cycle
Содержание SUPER S2DG2
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