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Super Motherboard User’s Manual
Enhanced Halt State (C1E)
Select Enable to use the "Enhanced Halt State" feature, which will signi
fi
cantly
reduce the CPU's power consumption by reducing the CPU's clock cycle and
voltage during a "Halt State." The options are Disable and
Enable
.
Chipset Con
fi
guration
North Bridge
This feature is used to con
fi
gure Intel North Bridge settings.
IIO (Integrated IO) Con
fi
guration
EV DFX (Device Function On-Hide) Features
When this item is set to Enable, the EV_DFX Lock Bits that are located on a
processor will always remain clear during electric tuning. The options are
Disable
and Enable.
IIO0 Con
fi
guration
IOU2 (IIO PCIe Port 1)
This feature allows the user to set the bus speed between the IOU2 and the
PCI-Exp port speci
fi
ed above. The options are x4x4, x8, and
Auto
.
IOU0 (IIO PCIE Port 2)
This feature allows the user to set the bus speed between the IOU0 and the
PCI-Exp port speci
fi
ed above. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8,
x16, and
Auto
.
IOU1 (IIO PCIE Port 3)
This feature allows the user to set the bus speed between the IOU1 and the
PCI-Exp port speci
fi
ed above. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8,
x16, and
Auto
.
No PCIe Port Active ECO
Use this feature to select a workaround setting to implement the engineering-
change order (ECO) on the system when the PCI ports speci
fi
ed by the user
are not active. The options are
PCU Squelch exit ignore option
and Reset the
SQ FLOP by CSR option.
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