Chapter 6: UEFI BIOS
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Adjacent Cache Line Prefetch
The CPU prefetches the cache line for 64 bytes if this feature is set to Disabled. The CPU
prefetches both cache lines for 128 bytes as comprised if this feature is set to Enabled. The
options are Disabled and
Enabled
.
Intel (VMX) Virtualization Technology
Use this feature to enable the Vantderpool Technology. This technology allows the system
to run several operating systems simultaneously. The options are Disabled and
Enabled
.
Active Processor Cores
This feature determines how many CPU cores will be activated for each CPU. When all is
selected, all cores in the CPU will be activated. The options are
All
and 1, 2, 3, 4, and 5.
BIST
Use this feature to enable the Built-in Self Test (BIST) at system reset or reboot. The options
are
Disabled
and Enabled.
AES
Select Enabled for Intel CPU Advanced Encryption Standard (AES) instructions support to
enhance data integrity. The options are Disabled and
Enabled
.
Boot Performance Mode
This feature allows the user to select the performance state that the BIOS will set before the
operating system handoff. The options are Power Saving,
Max Non-Turbo Performance
,
and Turbo Performance.
Intel® SpeedStep™
Intel SpeedStep Technology allows the system to automatically adjust processor voltage and
core frequency to reduce power consumption and heat dissipation. The options are
Disabled
and Enabled.
Intel® Speed Shift Technology
Use this feature to enable or disable Intel Speed Shift Technology support. When this feature
is enabled, the Collaborative Processor Performance Control (CPPC) version 2 interface will
be available to control CPU P-States. The options are
Disabled
and Enabled.
Monitor/Wait
Select Enable to enable the Monitor/Mwait instructions. The Monitor instructions monitors a
region of memory for writes, and Mwait instructions instruct the CPU to stop until the monitored
region begins to write. The options are Disabled and
Enabled
.C states
Use this feature to enable the C-State of the CPU. The options are Disabled and
Enabled
.
