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Super C9Z490-PG/-PGW User's Manual
Power LED Header
An onboard Power LED header is located at JLED1. This Power LED header is connected
to the Front Control Panel located at JF1 to indicate the status of system power. Refer to the
table below for pin definitions.
Power LED Header
Pin Definitions
Pin#
Definition
1
VCC
2
Connection to PWR LED in
3
Connection to PWR LED in
White Light LED Header
This 4-pin connector provides the connection to white light LED board inside the I/O cover. It
is located at JRLED1 on the motherboard. Refer to the table below for pin definitions.
White Light LED Header
Pin Definitions
Pin#
Definition
1
VCC
2
NC
3
NC
4
Ground
1. JLED1
2. JRLED1
PCH
PLX
Super I/O
LAN Controller
SW1
(CLEAR CMOS)
10G LAN
Controller
+
+
3
1
DESIGNED IN USA
C9Z490-PGW
REV:1.01
BIOS
LICENSE
MAC CODE
MAC CODE
BAR CODE
MH14
JRLED1
MH11
MH10
MH12
MH13
MH15
JSTBY1
JTPM1
HD AUDIO
B1
SP1
JD1
JSD1
SYS_FAN3
USB10/1
1 (3.2(5Gb))
JPW1
LED18
LED17
LED3
LED2
LED1
JPW2
JI2C2
JI2C1
JL1
LED4
JP
AC1
JLED1
JWD1
JPME2
12V_PUMP_PWR1
USB9 (3.2(20Gb))
USB8 (3.2(10Gb))
USB2/3
JF1
BOOT LED
VGA LED
DIMM LED
CPU LED
DP/HDMI
LAN1
AUDIO FP
COM1
USB0/1
PCIE M.2-M1
CPU SLOT1 PCI-E 3.0 X8 (IN X16)
CPU SLOT3 PCI-E 3.0 X16
PCH SLOT4 PCI-E 3.0 X1
CPU SLOT5 PCI-E 3.0 X8 (IN X 16)
I-SATA1
I-SATA0
I-SATA3
I-SATA2
CPU SLOT7 PCI-E 3.0 X16
SYS_FAN2
PCIE M.2-M2
USB12 (3.2(10Gb))
USB6/7 (3.2(10Gb))
USB4/5 (3.2(5Gb))
POWER
BUTTON
DIMMB1
DIMMB2
DIMMA1
DIMMA2
RESET
BUTTON
SYS_FAN1
CPU_FAN1
CLEAR CMOS
CPU_F
AN2
LAN2
PCIE M.2-E1
WiFi+BT
2
1