SIS Documentation
SIS3800
Scaler/Counter
Page 7 of 39
Control
XILINX
Counter
XILINX
VME
Interface
XILINX
Level Adaption
Driver/Receiver
Level Adaption
Driver/Receiver
Level Adaption
Driver/Receiver
Level Adaption
Driver/Receiver
VME Bus
4
4
4
4
Counter
XILINX
Level Adaption
Driver/Receiver
Level Adaption
Driver/Receiver
4
4
FLASH
PROM
File
Selection
Counter
XILINX
Level Adaption
Driver/Receiver
Level Adaption
Driver/Receiver
4
4
Counter
XILINX
Level Adaption
Driver/Receiver
Level Adaption
Driver/Receiver
4
4
SIS3800 Block Diagram
3.2 Counter Design and Modus Operandi
The counters are implemented in XILINX FPGAs. One of the counter FPGAs holds 8 32-bit
deep counter channels. The actual scaler contents are passed to the VME bus via a shadow
register. The scaler data have to be copied into the shadow register before readout via a
software command or a front panel hardware pulse. This can take place in parallel to the
acquisition of counts, what is called read on the fly. On a read on the fly the status of the
lowest 6 bits may be not accurate, i.e. the counter readout value is accurate modulo 64. (read
on the fly readout accuracy down to one count can be achieved with the SIS3801 multiscaler).
No pulses are missed during a read on the fly, i.e. the frontend continues counting. A diagram
of the setup is shown in the figure below. The different readout schemes are addressed in the
key register section.
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