SIS Documentation
SIS3800
Scaler/Counter
Page 17 of 39
8.4 Count disable register 0xC
The count disable register can be used to disable single channels or arbitrary groups of
channels. Note, that both the external (if used) and the internal conditions have to be in status
enable for the given channel.
The register is write only.
If bit N of the register is set, channel N+1 is disabled.
Example: If 0x5 is written to the count disable register, counting of channel 1 and 3 is
disabled.
8.5 Overflow registers 0x380, 0x3A0, 0x3C0, 0x 3E0
Each overflow register holds the overflow bit of eight counter channels (i.e. of one counter
XILINX) in its lowest eight bits.
Example: register 0x380 holds the overflow bits of channels 1-8 as shown in the table below.
Bit
31
30
29
28
27
26
25
24
Bits 23-1
Ch 8
Ch 7
Ch 6
Ch 5
Ch 4
Ch 3
Ch 2
Ch 1
undefined
8.6 Broadcast
Addressing
Broadcast addressing is an efficient way to issue the same command to a number of modules.
It can be used in A24 and A32 mode on SIS360x/38xx boards. The higher address bits are
used to define the broadcast class, the distinction of the modules is done via the A16 rotary
switch and the A_11 jumper. If broadcast addressing is used, the A32_U, the A_32_L, the
A24_U and the A24_L rotary switches must have the same setting in A32 mode, in A24
mode the A24_U and A24_L setting must be the same on all participating units. One of the
participating units must be configured as broadcast handshake controller by setting bit 7 in the
units control register. All of the participating units must have set bit 6 (enable broadcast) in
the control register. The broadcast time jitter was measured to be less than 40 ns within a
VME crate, i.e. you have the possibility issue commands under software control with a
maximum uncertainty of 40 ns (like clear all counters), what sure is worse, than a hard wired
front panel clear, but is much better than a VME single cycle loop over a number of units. The
four broadcast commands are executed via the VME key addresses at offset 0x030 through
0x3C.
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