SIS Documentation
SIS3800
Scaler/Counter
Page 8 of 39
Scaler Channel
Shadow
Register
Input
VME Interface
Control
VME Bus
Clock
Shadow
Clock
Shadow
External
VME Clock Shadow
Latch
3.3 Count Enable Logic
A channel acquires input or test counts, if the selective count enable and the global count
enable conditions are true. Via the test enable toggle bits in the control register the input of
the counter is switched to test pulses or front panel signals.
Scaler Channel N
Enable Scaler
AND
Count Enable
Selective Disable
Control Input Disable
MUX
MUX
OR
25 MHz reference (channel 1 only)
Input N
25 MHz test pulses
Single Test Pulse
External Test Pulse
3.4 Clear
Logic
The contents of the counters can be cleared via VME access or a front panel pulse. The four
possible clear sources are ored as shown in the diagram below.
Scaler Channel N
VME Selective Clear Channel N
VME Clear All
OR
External Clear
Clear
Clear after VME read
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