SIS Documentation
SIS3800
Scaler/Counter
Page 6 of 39
3 Technical
Properties/Features
The SIS3800 is rather a firmware design in combination with given board stuffing options,
than a name for the board (this is the reason, why the modules are named SIS360x/38xx on
the front panel and the distinction of the units is made by the module identifier register). The
firmware makes use of part of the possibilites of the SIS360x/38xx PCB, if the SIS3800 or
other firmware designs of the family come close to what you need, but something is missing,
a custom firmware design may be an option to consider.
Find below a list of key features of the SIS3800.
•
32 channels
•
200 MHz counting rate (ECL and NIM), 100 MHz for TTL
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32-bit channel depth
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NIM/TTL/ECL versions
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flat cable (TTL/ECL) and LEMO (TTL/NIM) versions
•
Shadow register
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Read on the fly
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A16/A24/A32 D16/D32/BLT32 (CBLT32 prepared)
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Base address settable via 5 rotary switches (A32-A12) and one jumper (A11)
•
VME interrupt capability
•
VIPA geographical addressing prepared
•
VIPA LED set
•
Reference Pulser Capability
•
Up to eight firmware files
•
single supply (+5 V)
3.1 Board
Layout
Xilinx FPGAs are the working horses of the SIS360x/38xx board series. The counter (prescaler,
latch, ...) logic is implemented in one to four chips, each chip handles eight front end channels.
The VME interface and the input and output control logic reside in two Xilinx chips also. The
actual firmware is loaded into the FPGAs upon power up from a FLASHPROM under jumper
control. The user can select among up to eight different boot files by the means of a 3-bit jumper
array. The counter and control inputs can be factory configured for ECL, NIM and TTL levels, on
the control outputs the same levels are the available as options. The standard SIS3800 version 1
design has no outputs implemented. The front panel is available as flat cable (ECL and TTL) or
LEMO (NIM and TTL) version. The board layout is illustrated with the block diagram below:
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