SIS Documentation
SIS3800
Scaler/Counter
Page 36 of 39
19.8 Row d and z Pin Assignments
The SIS3800 is prepared for the use with VME64x and VME64xP backplanes. Foreseen
features include geographical addressing and live insertion (hot swap). The prepared pins on
the d and z rows of the P1 and P2 connectors are listed below.
Position
P1/J1
P2/J2
Row z
Row d
Row z
Row d
1
VPC (1)
2
GND
GND (1)
GND
3
4
GND
GND
5
6
GND
GND
7
8
GND
GND
9
GAP*
10
GND
GA0*
GND
11
RESP*
GA1*
12
GND
GND
13
GA2*
14
GND
GND
15
GA3*
16
GND
GND
17
GA4*
18
GND
GND
19
20
GND
GND
21
22
GND
GND
23
24
GND
GND
25
26
GND
GND
27
28
GND
GND
29
30
GND
GND
31
GND (1)
GND (1)
32
GND
VPC (1)
GND
VPC (1)
Note: Pins designated with (1) are so called MFBL (mate first-break last) pins on the installed 160 pin
connectors, VPC(1) pins are connected via inductors.
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