SIS Documentation
SIS3800
Scaler/Counter
Page 24 of 39
14 Control Input Modes
The assignment of the control inputs can be controlled via the input mode bits in the control
register. While the standard SIS3800 firmware design (design 3800 version 1) has inputs
only, design 3800 version 2 is compatible with board, where control lines 5 to 8 are
configured as outputs (what is the case for SIS3801 multiscaler boards).
14.1 Version 1
Control Input Modes
Mode 0 (bit1=0, bit0=0):
all control inputs are disabled
Mode 1 (bit1=0, bit0=1):
input 1 -> disable count all channels
input 2 -> clear all channels
input 5 -> external clock shadow register
input 7 -> external test pulse (max 50 MHz)
Mode 2 (bit1=1, bit0=0):
input 1 -> disable count channels 1-16
input 3 -> disable count channels 17-32
input 2 -> clear channel 1-16
input 4 -> clear channel 17-32
input 5 -> external clock shadow register
input 7 -> external test pulse (max. 50 MHz)
Mode 3 (bit1=1, bit0=1):
input 1 -> disable count channels 1-8
input 3 -> disable count channels 9-16
input 5 -> disable count channels 17-24
input 7 -> disable count channels 25-32
input 2 -> clear channels 1-8
input 4 -> clear channels 9-16
input 6 -> clear channels 17-24
input 8 -> clear channels 25-32
14.2 Version 2 and 3
Control Input Modes
Mode 0 (bit1=0, bit0=0):
all control inputs are disabled
Mode 1 (bit1=0, bit0=1):
input 1 -> disable count all channels
input 2 -> clear all channels
input 3 -> external clock shadow register
input 4 -> external test pulse (max 50 MHz)
Mode 2 (bit1=1, bit0=0):
all control inputs are disabled
Mode 3 (bit1=1, bit0=1):
all control inputs are disabled
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