Hardware layout and configuration
UM1855
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DocID027351 Rev 3
2.22.1 Limitations
•
FMC_NWAIT and SAI1_SDA signals are mutually exclusive.
•
The NOR Flash memory device’s addressable space is limited if some or all of A19,
A20, A21, A22 and A23 FMC address lines are shunted to the CN12 connector for
debug trace purposes. In such a case, the disconnected addressing inputs of the NOR
Flash memory device are pulled down by resistors.
Section 2.2
provides information on
the associated configuration elements.
2.22.2 Operating
voltage
NOR Flash memory operating voltage must be in the range from
1.65 V to 3.6 V.
2.23 EEPROM
M24128-DFDW6TP, a 128-Kbit I²C-bus EEPROM device
,
is fitted on the main board of
STM32L476G-EVAL, in U6 position. it is accessed with I²C-bus lines I2C2_SCL and
I2C2_SDA of STM32L476ZGT6. It supports all I²C-bus modes with speeds up to 1 MHz.
The base I²C-bus address is 0xA0. Write-protecting the EEPROM is possible through
opening the SB7 solder bridge. By default, SB7 is closed and writing into the EEPROM
enabled.
2.23.1 Operating
voltage
The M24128-DFDW6TP EEPROM device’s operating voltage must be in the range from
1.7 V to 3.6 V
2.24 RF-EEPROM
RF-EEPROM daughterboard, ANT7-M24LR-A, can be connected to CN3 connector of the
STM32L476G-EVAL board. STM32L476ZGT6 can access the RF-EEPROM in two ways,
Table 25. NOR Flash memory-related configuration elements
Element
Setting
Configuration
JP13
JP13
Default setting.
NOR Flash memory write is enabled.
JP13
NOR Flash memory write is inhibited. Write protect is activated.
R53
SB10
R53 In
SB10 open
Default setting.
PD6 port of STM32L476ZGT6 is used for SAI1_SDA signal and routed
to audio codec.
NOR Flash memory device’s status register can be accessed.
R53 Out
SB10 closed
PD6 port of STM32L476ZGT6 is used for FMC_NWAIT signal and
routed to NOR Flash memory device’s RB port.
NOR Flash memory device’s status register cannot be accessed.
