Hardware layout and configuration
UM1855
56/100
DocID027351 Rev 3
Figure 17. Schematic diagram of the analog part of IDD measurement
2.30.2 Low-power-mode
IDD
measurement principle - logic part
The target microcontroller can only carry out actions for measuring a voltage when in
dynamic run mode. This is the reason why, voltage representing the current consumed by
the microcontroller when in low-power mode needs to be held by a sample-and-hold circuit,
for being exploited by the microcontroller at a later time, when back in dynamic run mode.
The sample-and-hold (S&H) circuit is built with U13 switch, R122 resistor and C73 sampling
capacitor.
The measurement of low-power-mode current consumption is started and end by the
microcontroller in its dynamic run mode. As, between the start and end event, the
microcontroller must transit through one of its low-power modes, an extra logic is required to
time and control events during this state. It consists of U14 counter, U16 inverter and the
transistor T3.
Figure 18
shows the corresponding schematic diagram.
VDD
R135
1[1%]
R123
1K[1%]
3
4
5
G
S
D
1
2
6
T2
FDC606P
VDD_MCU
R136
3K6 0.1%
R125
3K6 0.1%
R129
180K 0.1%
R132
180K 0.1%
GND
+5V
C75
100nF
GND
GND
decoupling capacitor
close from TSZ124 part
1
4
3
2
11
V+
V-
U15A
TSZ124IPT
7
5
6
U15B
TSZ124IPT
14
12
13
U15D
TSZ124IPT
8
10
9
U15C
TSZ124IPT
R128
22K
R124
1K
Shunt_x1000
Current
direction
to MCU
bypass path
current
measurement
path
differential
amplifier
shunts
C144
100nF
GND
1
2
3
4
JP11
Current
direction
VDD from
power
supply
