Hardware layout and configuration
UM1855
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DocID027351 Rev 3
Sources of reset are:
•
reset button B1
•
JTAG/SWD connector CN15 and ETM trace connector CN12 (reset from debug tools)
•
through extension connector CN7, pin 32 (reset from daughterboard)
•
ST-LINK/V2-1
•
RS-232 connector CN9, terminal 8 (CTS signal), if JP9 is closed (open by default)
2.6 Boot
2.6.1 Boot
options
After reset, the STM32L476ZGT6 MCU can boot from the following embedded memory
locations:
•
main (user, non-protected) Flash memory
•
system (protected) Flash memory
•
RAM, for debugging
The microcontroller is configured to one of the listed boot options by setting the
STM32L476ZGT6 port BOOT0 level by the switch SW1 and by setting nBOOT1 bit of
FLASH_OPTR option bytes register, as shown in
Table 5
. Depending on JP8, BOOT0 level
can be forced high and, SW1 action overruled, by DSR line of RS-232 connector CN9, as
shown in
Table 6
. This can be used to force the execution of bootloader and start user Flash
memory flashing process (ISP) from RS-232 interface.
The option bytes of STM32L476ZGT6 and their modification procedure are described in the
reference manual RM0351. The application note AN2606 details the bootloader mechanism
and configurations.
Table 5. Boot selection switch
Switch
Setting
Description
SW1
Default setting
.
BOOT0 line is tied low. STM32L476ZGT6 boots from user Flash
memory.
BOOT0 line is tied high. STM32L476ZGT6 boots from system Flash
memory (nBOOT1 bit of FLASH_OPTR register is set high) or from
RAM (nBOOT1 is set low).
Table 6. Bootloader-related jumper setting
Jumper
Setting
Description
JP8
JP8
Default setting
.
BOOT0 level only depends on SW1 switch position
JP8
BOOT0 can be forced high with terminal 6 of CN9 connector (RS-232
DSR line). This configuration is used to allow the device connected via
RS-232 to initiate STM32L476ZGT6 flashing process.
