MACH16
S
LIM
L
ITE
3Gbps
SATA
S
TANDARD
S
OLID
-S
TATE
D
RIVE
P
ART
N
UMBER
:
M16SD2S(3)-
XXX
U(T)(X)-XXX
D
OCUMENT
N
UMBER
:
61000-07132-311
R
EVISION
N
UMBER
:
3.11
R
EVISION
D
ATE
:
01/15/2013
23
S
ECURE
A
RRAY OF
F
LASH
E
LEMENTS
™
(S.A.F.E.)
T
ECHNOLOGY
Secure Array of Flash Elements™ or S.A.F.E. Technology is a proprietary technology implemented in the
controller that is designed to overcome the risk of page or block failures over the given lifetime of the
flash. An integrated parity protection engine will recover data and automatically relocate it to good known
blocks in the flash array when the flash controller encounters uncorrectable data errors. NAND flash can
suffer cascading page and block failures that can produce uncorrectable data errors. These data errors
are further affected by flash die geometry reductions that result in potentially higher bit errors in the flash
media. The problem is further compounded by the number of flash components that are actually installed
in the SSD (e.g. the reliability of the SSD decreases as the number of flash devices increases). OEMs will
not accept an Annualized Failure Rate (AFR) of greater than 0.5% and S.A.F.E. is required to support
that AFR with 4Xnm and lower geometries.
B
AD
-B
LOCK
M
ANAGEMENT
The bad-block mapping scheme will detect faulty blocks during operation. Bad blocks are flagged in a
defect list. Blocks added to the defect list are excluded and never used for data storage.
B
UILT
-I
N
S
ELF
-T
EST
The micro-controller tests the controller memory during power-up, and then performs a back-end status
check to verify proper flash memory controller operations. If a fault condition is detected in the flash
memory controller, the status of the SSD is reported as failed.
E
NDURANCE
The product life of a SLC-based SSD is at least three (3) years, and at least one (1) year for a MLC-
based SSD.
E
RROR
D
ETECTION AND
E
RROR
C
ORRECTION
The Error Detection Code and Error Correcting Code (EDC/ECC) will maintain data integrity by allowing
single or multiple bit corrections to the data stored in the flash array. If the data is corrupted due to aging
or during the programming process, EDC/ECC will compensate for the errors to ensure the delivery of
accurate data to the host computer. The 32-bit EDC/ECC engine is capable of correcting 32 random bits
in error per 512 bytes. A retry algorithm is also implemented so that single event disturbances such as
ESD or EMF occurring during a read operation can be readily overcome.
E
RROR
R
ATES
Table 3 lists the error limit specifications. When all data correction mechanisms are enabled, the error
rate will be sustained through all operating temperature ranges as specified in the following sections.
Table 3: Error Limit Specifications
E
RROR
T
YPE
M
AXIMUM
N
UMBER OF
E
RRORS
Recoverable Data Error
1 bit in 10
17
Unrecoverable Data Error
Less than 1 bit in 10
17
F
IRMWARE
U
PDATES
The maximum allowable number of firmware updates is 100.
