SST-PFB3-PCI
Hardware Reference Guide
3.2 SST-PFB3-PCI Configuration Space
Table 13: SST-PFB3-PCI Configuration Space
PCI CFG
Register
Address
Register Function
31 24 23 16 15 8 7 0
PCI
Writable
0x00 Device
ID
0x0033
Vendor ID
0x133D
N
0x04 Status
Command
Y
0x08
Class Code
Revision ID
N
0x0C
BIST
Header ID
PCI Latency
CacheLineSize
Y[7:0]
0x10
PCI Base Address 0
Memory, 128 bytes, Reserved
Y
0x14
PCI Base Address 1
Not Used
Y
0x18
PCI Base Address 2
Memory, 256K bytes
Profibus Interface
Refer to the relevant firmware documentation for details.
Y
0x1C
PCI Base Address 3
Memory, Host Interface Registers
See Section 3.1,
PFB3-PCI Card Configuration Registers
, for details.
Y
0x20
PCI Base Address 4
Not Used
Y
0x24
PCI Base Address 5
Not Used
Y
0x28
Cardbus CIS Pointer (Not Supported)
N
0x2C
Subsystem Device ID
0x9030
Subsystem Vendor ID
0x10B5
N
0x30
PCI Base Address for Local Expansion ROM
Y
0x34 Reserved N
0x38 Reserved N
0x3C
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
Y[7:0]
Note
Refer to the PCI specification and your particular OS documentation for the function of
all other PCI configuration space registers and their typical uses.
Hardware Register Details
29
©2003 Woodhead Software and Electronics, a division of Woodhead Canada Limited.
Document Edition: 1.0, Document #: 715-0060, Template Edition: 1.0, Template #: QMS-06-045.
Use, duplication or disclosure of this document or any of the information contained herein is subject to the restrictions on page ii of this document.
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