Hardware Reference Guide
SST-PFB3-PCI
Table 6: Control Register Bit Descriptions
Bit Name
Description
CardRun
This bit controls and indicates whether or not the card’s processor is running. It also affects the
card’s SYS LED.
•
When this bit is 0, the processor is halted, and the SYS LED is RED
•
When this bit is 1, the processor is running normally, and the LED is under processor
control
•
When this bit is 1, and watchdog has timed out, processor is halted, and the SYS LED
is RED
This bit must remain low for at least 50
µ
s to guarantee proper reset.
MemEn
High (1) enables shared memory decoding of addresses in this board’s range. This board’s
range is defined by the plug and play BIOS or operating system.
IntEn
High (1) enables interrupts on IrqLevel when a HostIrq bit is high (1).
•
Writing 1 enables interrupts
•
Writing 0 disables interrupts (the IrqPending flag still functions as described)
WdTout
WdTout high (‘1’) indicates that a watchdog timeout has occurred, or that the CPU has been
held in RESET by some other means. To restore this bit to 0, clear CardRun.
HostIrq1
This bit is used by the card processor to send interrupts to channel 1 of the host
•
Writing 1 acknowledges the interrupt and clears it
•
Writing 0 has no effect
•
Reading 1 indicates interrupt in progress
•
Reading 0 indicates interrupt complete
HostIrq0
This bit is used by the card processor to send interrupts to channel 0 of the host
•
Writing 1 acknowledges the interrupt and clears it
•
Writing 0 has no effect
•
Reading 1 indicates interrupt in progress
•
Reading 0 indicates interrupt complete
CardIrq1
This bit is used by the host to send interrupts to channel 1 of the card processor
•
Writing 1 generates an interrupt to the card
•
Writing 0 has no effect
•
Reading 1 indicates interrupt in progress
•
Reading 0 indicates interrupt complete
CardIrq0
This bit is used by the host to send interrupts to channel 0 of the card processor
•
Writing 1 generates an interrupt to the card
•
Writing 0 has no effect
•
Reading 1 indicates interrupt in progress
•
Reading 0 indicates interrupt complete
26
Hardware Register Details
©2003 Woodhead Software and Electronics, a division of Woodhead Canada Limited.
Document Edition: 1.0, Document #: 715-0060, Template Edition: 1.0, Template #: QMS-06-045.
Use, duplication or disclosure of this document or any of the information contained herein is subject to the restrictions on page ii of this document.
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