SST-PFB3-PCI
Hardware Reference Guide
3.1.3 AddrMatch Register
Table 7: AddrMatch Register Bit Descriptions
Bit Name
Description
AM19 – AM12
Reserved. This register always reads zero, and writing these bits has no effect.
3.1.4 WinSize Register
Table 8: WinSize Register Bit Descriptions
Bit Name
Description
WS19-WS12
Reserved. This register always reads 0x3F, and writing this register has no effect.
3.1.5 Bank Address Register
This register is used to switch banks of shared memory into host memory space.
Table 9: Bank Address Register Bit Descriptions
Bit Name
Description
BA17-13
Reserved. This register always reads zero, and writing these bits has no effect.
3.1.6 HostIrq Register
Table 10: HostIrq Register Bit Descriptions
Bit Name/ Value
Description
IrqLevel3-IrqLevel0
Reserved. This register always reads zero, and
writing this register has no effect
Hardware Register Details
27
©2003 Woodhead Software and Electronics, a division of Woodhead Canada Limited.
Document Edition: 1.0, Document #: 715-0060, Template Edition: 1.0, Template #: QMS-06-045.
Use, duplication or disclosure of this document or any of the information contained herein is subject to the restrictions on page ii of this document.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com