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B i t 2 : th i s b i t spec i f i e s the numbe r of �s top b i t s in each transm i t t e d o r
rece i ve d s e r i a l charac t e r . I f b i t 2 i s
·
a log ic 0 , 1 S t op b i t i s gene rated o r
checked in the t ransm i t o r re ce ive data , re spec t i ve l y . I f b i t 2 i s a l og i c 1
wh en a 5-b i t word leng th i s se l e c t e d v ia b i t s 0 and 1 , 1 - 1 / 2 S t op b i t s are
gene r a t e d or checked .
I f b i t 2 i s a logic 1 whe n e i t he r a
6 ,
7 , or 8-b i t wor d
l ength
i s
se l ec te d , 2 S t op b i t s a re gene r a t e d or checked .
B i t
3 :
Th i s b i t i s the Par i t y Enab l e b i t . When b i t 3 i s a logic 1 , a Par i t y
b i t i s gene r a t e d ( t ransm i t data ) or checke d ( rece i ve d a ta ) be tween the l a s t
dat a wo r d b i t and S top b i t of t h e se r ia l dat a .
( T he Par i t y b i t i s u s e d to
p roduce an even or o dd number of l s when the d a ta word b i t s and the P a r i ty b i t
are summe d ) .
B i t 4 : Th i s b i t i s the Even Par i t y S e l ec t b i t .
When b i t 3 i s
a
log ic 1 and
bit 4 is a log ic 0 , an odd number of log ic l s i s t ransm i t te d or checked in the
dat a wor d b i t s and Pari t y b i t . Whe n b i t 3 is a log ic 1 and b i t 4 is a logic 1 ,
an even numb e r o f b i t s i s t ransm i t te d or checked .
B i t 5 : Th i s b i t i s the S t i ck Par i t y b it . When b i t 3 i s a logic 1 and b i t
5
i s
a log ic 1 , t he P a r ity b i t i s t ransm i t te d and then d e t ected b y the rece i ve r as a
l o g ic 0 i f b i t 4 i s a logic 1 or as a log ic 1 i f b i t 4 a l og i c 0 .
B i t
6 :
T h i s b i t i s t he S e t Break Con t r o l b i t . When b i t
6
i s a log ic 1 , the
se ria l output ( SOUT ) is forced to the Spac ing ( logic 0) s t a t e and rema ins the re
reg a r d l e s s of other t ransm i tt er a c t i v i ty
.
The s e t b reak i s d i sab l e d by s e t t ing
b i t 6
to a log ic 0 . Th i s f e a ture enab l e s the CPU to a l e r t a term ina l in a
comp u t e r commun i c a t ions s y s tem.
Bit 7 : Th i s b i t i s the D iv i so r Latch Acc� s s Bit ( DLAB ) .
I t mus t be set h igh
( log ic
1 )
to acce s s t he D iv i sor Latches of the B a ud Rate Gene rator dur ing a
Rea d or Wri t e ope ra t i on .
I t mus t be se t low ( l ogic 0 ) to acce s s the Rece ive r
Bu f f e r , the T ransm it t er Ho l d ing Reg i s t e r , or t he I nt e r r upt Enab l e Reg i s t e r .
INS8 2 50
Baud Ra te Gene rator
The INS8 250 conta ins a p rogrammab l e Baud Ra te Gene r a t o r tha t i s capab l e of
tak ing any c l ock input ( DC t o 3 . 1 MHz ) and d i v i d ing i t by any divi sor f rom 1 t o
( 2 1 6
1 ) . The o
u
tput f re quency of the Baud Gene ra t o r is 1 6 x t h e Baud ra t e
[
divi s or #
=
( f re quency input ) - ( baud r a t e x 1 6 ) ] . Two 8-b i t l atches s tore
the d i v i sor in a 1 6-b i t b inary forma t . The se D iv i sor Latche s mus t be loaded
du r ing i n i t i a l i z a t i on in order to i nsure de s i re d ope ra t i on of the Baud Rat e
Gene rator .
Upon loading e i ther o f the Div i sor Latche s , a 1 6-b i t Baud counter
i s imme d ia t e l y l oade d . Th i s previouss l ong counts on init i a l l oa d .
4 . 60
Содержание MKI
Страница 1: ...SERVICE TECHNICAL MANUAL VOL 1 l SVI318 328 MKI MKII COMPUTER SYSTEM SVI SPECTRAVIDEO ...
Страница 7: ...4 Remove the seven retaining screens 5 Remove the cover 2 2 ...
Страница 8: ...6 Remove the screens on the metal cover 7 Remove the metal cover 2 3 ...
Страница 9: ...To r e assemble u se the above procedures in the rever se order 2 4 ...
Страница 134: ...5 CIRCUIT SCHEMATIC AND COMPONENT LAYOUT 5 1 ...