Spectravideo MKI, Сервисное – Техническое руководство

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MI
MREQ
NMI
RD
---
RE SET
RFSH
WA IT
Mach ine Cyc l e One ( output , act ive Low) .
MREQ , indicates that tbe cur rent machine
fetch cyc l e of an inst ruct ion execut ion .
indicat e s an interrupt acknowl edge
together with
c�l e i s the opcode
Ml , together with
cyc l e .
Memory Request ( ou tput , act ive Low , 3-st ate ) . MREQ indicates
that the addre s s bus ho l d s a va l i d address for a memory read
or memory wr i te operat ion .
Non-Maskab l e Interruf!_( inpu t , ac t i ve Low) . NMI has a h ighe r
p r i or i t y than INT . NMI is alway s recogn i zed at the end o f
the current ins t r uc t i on , independent of the sta t us of the
interrupt enab l e f l ip-f l op , and a u toma t ica l ly f orces the CPU
to re s t a r t at loca t ion 0066 H .
Memory Read ( ou tp u t , ac t ive Low , 3-state ) . RD indicates
the CPU wan t s to read data f rom memory or an 1 /0 device .
add re ssed I / 0 dev i ce or memory should use th i s s i gna l to
9ata on to the CPU data b us .
Re set ( inpu t , a c t i ve Low) . RESET i n i t i a l izes t he CPU a s
fo l lows :
tha t
The
gate
It re se t s the interrupt enab l e f l ip-f lop , clears the PC and
Reg i s ters I and R , and sets the int errupt s ta t us to Mode 0 .
Dur i ng re set t i me , the addre s s and data bus go to a h igh­
impendance sta te , and al l cont rol ou tput s igna l s go to the
ina c t i ve s t a t e . Note that RESET must be act i ve f or a
min imum of three fu l l c l ock cyc l e s be fore the re set ope ra t i on
is comp l e te d .
Re fresh ( output , act ive Low) . RFSH , toge ther w i th MREQ ,
ind ica t e s that the lower seven b i t s of the system ' s address
b us can be used as a re f re sh a ddress to the system ' s dynam ic
memo r ies .
Wai t ( input , ac t i ve Low) . WAIT indica tes to the CPU tha t the
a ddre s se d memory or I / 0 devices a re not ready for a data
t rans f e r . The CPU cont i nues to enter a Wa i t s t a te as long as
th i s s i gna l i s ac t ive . Extended WAIT periods can p revent the
CPU f rom re f re sh ing dynam ic memory p roper l y .
Memory Wr i te ( ou t pu t , act ive Low , 3-state ) . WR indicates that
the CPU data bus ho lds va l id data to be store d at the addre s se d
memory or I /O location .
4 . 3B